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Design >> RF Design >> Fully Differential Impedance Matching
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Message started by yousuf on Sep 13^th, 2010, 3:53pm

Title: Fully Differential Impedance Matching
Post by yousuf on Sep 13^th, 2010, 3:53pm

Hello,
I am designing a regular fully differential amplifier at 2.5GHz, nmos
input stage and pmos loads. I am having difficulties with matching the
output to 50 ohms.

When I try to connect a port to the output node, I measure a negative
real resistance. I do not know what is happening.

The same thing happened when I tried to measure the input impedance but I just used one port with the +end of the port connected to the +input amplifier node and the -end to the port connected to the -input of the amplifier, and it worked for the input. Sadly I cannot get it work for the output.

I have also tried to put a Balun but nothing seems to work.

Please find the pictures of the schematic and real impedance measured at the output. I would greatly appreciate if some on can help me figure out the correct setup to measure the output impedance, without getting this -ve real impedance.

In the Amplifier all transistors are operating in the saturation region, both nmos current and pmos currents are balanced (Although I will need a CMFB to ensure that, which I will Put together later, my real concern at the moment is the design of the impedance matching network and correct measurement of the output resistance)

Circuit Schematic

http://i51.tinypic.com/3y3it.png

Real Part of the output impedance

http://i52.tinypic.com/345ou53.png

Regards
Yousuf

Title: Re: Fully Differential Impedance Matching
Post by vp1953 on Sep 13^th, 2010, 4:44pm

Hi Yousef,

Negative impedance can possibly arise via gate drain parasitic capacitance.

- are you able to run transient simulations at these frequencies without any oscillations or other problems - in other words, the amplifier behaves as an amplifier at the frequencies of interest?

- can you try putting a large capacitor (1uf) at the gates of the input transistors (between the gate and gnd). Is the impedance still negative with these capacitors

Title: Re: Fully Differential Impedance Matching
Post by yousuf on Sep 13^th, 2010, 11:27pm

Hi vp1953,

Here are the results that I got systematically.

First without any impedance matching networks. I am getting real impedance at both the input and the output. So I believe the amplifier is working fine

circuit diagram
http://i54.tinypic.com/2lnfehg.png

real impedance at the input and output
http://i56.tinypic.com/ehzqc3.png

Then I make the input impedance matching network and things get weird. Below is the S11 and the output impedance ( comes out negative )

S11 input
http://i56.tinypic.com/33mwf8p.png

Output impedance with input matching in place ( coming out negative)
http://i55.tinypic.com/fay1r7.png

circuit diagram
http://i56.tinypic.com/2po5b9d.png

Then I decide to make the output impedance matching first. Again comes out weird. This time the input impedance is negative.

circuit diagram
http://i52.tinypic.com/vpewl2.png

negative impedance at input
http://i55.tinypic.com/x55x5i.png

S22 at output
http://i55.tinypic.com/x55x5i.jpg

I think as soon as I put the matching network things stray out. I believe the simulator cannot recognize that it is a fully differential network.

Once again I really appreciate any help or suggestions

Regards

Yousuf

Title: Re: Fully Differential Impedance Matching
Post by aaron_do on Sep 14^th, 2010, 7:27am

Hi Yousuf,

I think vp1953 is right.

Also, in your case, your reverse isolation is poor due to the coupling between the gate and drain through Cgd. Therefore you cannot design your impedance matching networks one at a time. The common way around this is to use a cascode structure, however there are other techniques such as neutralization which may help.

cheers,
Aaron