The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> how to understand this curve?
https://designers-guide.org/forum/YaBB.pl?num=1284467830

Message started by lhlbluesky_lhl on Sep 14th, 2010, 5:37am

Title: how to understand this curve?
Post by lhlbluesky_lhl on Sep 14th, 2010, 5:37am

i have designed a two stage opamp (used for a buffer, fck=15M, CL=12pF), the first stage is folded cascode, the second is common source, and i use cascode compensation to ensure frequency stability, now, i get the following simulation curve, when the input signal from 0.4 to 1.6, it settles well, but when the input signal from 1.6 to 0.4, it has a very big overshoot, why? the PM is 70 deg or so, and it is not like normal underdamped oscilation, what is the reason of this big overshoot? please give me some advice, thanks all.

Title: Re: how to understand this curve?
Post by lhlbluesky_lhl on Sep 14th, 2010, 5:40am

the black curve is the input signal, the blue curve is the output curve, please help me, thanks.

Title: Re: how to understand this curve?
Post by vp1953 on Sep 14th, 2010, 4:32pm

Hi Lhlbluesky_lhl,

It is not unusual that for large input signals, the transfer function can be different for input signal going low to high and high to low.

- can you plot similar curves when input varies from say 0.4 to 0.6?
- also please provide plots when input varies from 1.4 to 1.6
- is your 1.6V close to supply voltage (if yes, it is possible that the impedance of the current loads are reduced, pushing one of the poles further out and causing the underdamped behaviour)

Title: Re: how to understand this curve?
Post by RobG on Sep 15th, 2010, 8:11am

Too little info. Can you elaborate on your output stage? Also, what sort of differential pair do you have?

That funny ringing when the signal is going low is probably caused by a zero partially countering a pole. With cascode compensation this can happen if the gm of the output stage is large compared to the gm of the cascode device. I could see this happening if you just have an NMOS output stage biased with a current source.

rg

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.