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Design Languages >> Verilog-AMS >> Transient simulation of Verilog-A model - Explanation required
https://designers-guide.org/forum/YaBB.pl?num=1284716414

Message started by kumar on Sep 17^th, 2010, 2:40am

Title: Transient simulation of Verilog-A model - Explanation required
Post by kumar on Sep 17^th, 2010, 2:40am

Hallo All,

I have simulated a D-latch using OFET. When running a transient simulation it gave me the following warnings.

"Matrix is singular (detected at `NQ')"

"Zero diagonal at net1 and net1"
Then the simulation ended prematurely with convergence problem. Now I ran the simulation using a cmin of 1fF and then the zero diagonal warning disappeared and the circuit also converged. But the first warning is still there. I am giving a pulsed input to DIN but the output of the latch (Q and NQ) doesn't change. Is this error due to cmin or the first warning? I know that cmin is used at all floating nodes to avoid convergence problem. But does cmin affect the functionality of the circuit? I have attached the model(with parameters input file) and schematic. The inputs used are as follows.

DIN - pulse (-0.2 , -14 V); CLK - pulse (-0.2, -10.2V, freq = 100Hz) ,NCL- negated CLK

Title: Re: Transient simulation of Verilog-A model - Explanation required
Post by Geoffrey_Coram on Sep 22^nd, 2010, 5:39am

Your code appears to set I(d,s) <+ 0 if (vds >= 0).

This seems completely wrong to me. I don't know what an "OFET" is, but the way you've drawn your schematic leads me to believe vds>=0 is the "normal" way the device is connected, and thus both devices will be completely off, presenting no conduction path for the node inv_op of inv_sch.png. Model writers will often put in a GMIN term to provide some minimal conductance.

Title: Re: Transient simulation of Verilog-A model - Explanation required
Post by kumar on Sep 22^nd, 2010, 6:36am

Hello Coram,
Thank you for your reply. Please note that the Vdd is -15V and the OFET is normally ON transistor. i.e it is ON even for Vgs = 0V... The output of INV switch between few mV and -14.75V.. The D terminal of load is -15V , S is few mV to -14.75V. So the Vds is not >= 0.. Similarly the S terminal of driver is 0V, D is mV to -14.75V. So teh Vds is not >= 0. Anyhow I will try to chk the schematic thoroughly..

Title: Re: Transient simulation of Verilog-A model - Explanation required
Post by Geoffrey_Coram on Sep 24^th, 2010, 1:49pm

Well, OK, but still, if the simulator somehow gets to the point where it thinks vds > 0 (perhaps Newton's method ends up overshooting the origin), then your model provides no information about how to get back to a reasonable solution.