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Design >> Mixed-Signal Design >> Algorithmic (Cyclic) ADC
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Message started by sunny_77ir on Sep 19^th, 2010, 10:05am

Title: Algorithmic (Cyclic) ADC
Post by sunny_77ir on Sep 19^th, 2010, 10:05am

Hi Guys,
I'm looking for a through tutorial about "algorithmic (cyclic) analog to digital converter" which can also help to design it.

Title: Re: Algorithmic (Cyclic) ADC
Post by ywguo on Sep 20^th, 2010, 2:34am

You can google and search on the IEEExplore. This is one -- A CMOS 13-b cyclic RSD A/D converter -- by Ginetti, B. ; Jespers, P.G.A. ; Vandemeulebroecke, A. . The paper is presented on July 1992 issue of JSSC.

Title: Re: Algorithmic (Cyclic) ADC
Post by carlgrace on Sep 24^th, 2010, 4:03pm

Most design lore associated with pipelined ADCs is applicable to algorithmic ADCs. Another good resource is the JSSC paper from Erdogan (I think it was in 1999).

Title: Re: Algorithmic (Cyclic) ADC
Post by loose-electron on Oct 24^th, 2010, 6:16pm

carlgrace wrote on Sep 24^th, 2010, 4:03pm:

Most design lore associated with pipelined ADCs is applicable to algorithmic ADCs. Another good resource is the JSSC paper from Erdogan (I think it was in 1999).

Agreed - this is a good surce of knowledge here - think the first stage of a pipeline for noise and accuracy.