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Design >> Analog Design >> power-down strategy
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Message started by carlgrace on Sep 24^th, 2010, 4:02pm

Title: power-down strategy
Post by carlgrace on Sep 24^th, 2010, 4:02pm

What strategy for power down are you guys using for your analog circuits? Do you make sure every node is pulled high or low, or just the gates? For example, in an opamp, do you just kill it's bias circuit, or do you also make sure all the transistor drains are at one supply or the other (depending on if they are N or P devices)?

Carl

Title: Re: power-down strategy
Post by wave on Sep 24^th, 2010, 5:35pm

Carl - you have to be concerned with every node. Generally turning off the biases will get you 80% there. Then 20% will be remaining nodes floating that should be tied off.

The bug I've frequently seen is a high impedance node created by this strategy and overlooked as the simulator drove it one way (low or high); that shut down a follow-on node. In face, that Hi-Z node can float anywhere causing the follow-on node to draw power. Drains of comparators are a common place for this, since you asked about Gates.

Good luck,
Wave

Title: Re: power-down strategy
Post by raja.cedt on Sep 25^th, 2010, 5:30am

hi carl,
it depends on the type of application and till what extent you want power down safely. As wave told if you power down bias nodes means by connecting to vss or vdd you would be in a safe position. But it is always good practice is to pull down or pull up all possible nodes like tail node in diff pair and pass transistor gate node in the regulator. Don't put so many power downs....some times power down transistors from vdd as well as vss may create a low impedance path from vdd to vss (once this happen to me)

Thanks.

Title: Re: power-down strategy
Post by avlsi on Sep 25^th, 2010, 7:00am

I partially disagree with every node being pulled to high or low. Let us take the case of a regulator which gives 1.2 V output on the pad. In case if we want overdrive the whole chip with external supply, then the regulator must be disabled and the output must be at high impedance.
So it depends on each circuit. Defacto would be to leave of voltage sources like regulator outputs at high impedance so that we force them externally.

Title: Re: power-down strategy
Post by carlgrace on Sep 27^th, 2010, 11:26am

Wave, Alvsi,

This was my thinking too. If you leave a node floating, it might drift enough to turn on a device. So what I have been doing is forcing every node that isn't overridden. I was asking what other people did because all those switches become a bit of a pain in layout.

Thanks everyone,
Carl

Title: Re: power-down strategy
Post by RobG on Sep 27^th, 2010, 4:10pm

In 18 years I've never felt it was necessary to tie down drains -- maybe if it was rad-hard or something special. A tri-state buffer floats the drains so I'm not sure what the problem would be.

But I definitely tie down the gates.

rg