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Design Languages >> Verilog-AMS >> Tristate output of Analog value
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Message started by sand_dolphin2 on Sep 27^th, 2010, 12:22am

Title: Tristate output of Analog value
Post by sand_dolphin2 on Sep 27^th, 2010, 12:22am

Hi there,　i'm digital engineer.

Plz let me know about how 2 coding verilo-AMS.

Now i make test bench for checking inout I/O behavior.
For checking output behavior of I/O,
test bench which is connected to this I/O have to stop driving
like as tri state buffer of Logic for checking I/O's output signal.

now my test bench was made by Verilog-D coding,
and DUT had 5V I/O (analog schematic design).

in this case, i should change digital 2 Analog converter
like here

module DAC_ams( Din , A5vout );

input Din;
output A5vout;

electrical Din,A5vout;

real temp;

analog begin
@(cross(V(Din)-0.7,0));
if(V(Din)>0.1) temp = 1;
else temp=0;

V(A5vout) <+ 5*transition(temp,0,1n,1n);

end

endmodule

when Logic test bench drive Hiz, this module stop driving too.

plz let me know how 2 correct this module for this aim ?

::)

Title: Re: Tristate output of Analog value
Post by sheldon on Sep 27^th, 2010, 1:26am

Sand Dolphin,

It appears that your module always outputs a 5V
If the V(Din) [rising edge]> 0.7 --> V( A5vout) = 5
If the V(Din) [falling edge] < 0.7 --> V( A5vout) = 5
since V(Din) > 0.1

The V(Din) is only checked at the cross level. It seems like you need
to add two functions,
1) Method to define when to be in Hi-Z state
2) A HiZ output state

I am not sure that you can use the output level of the previous
module to define a HiZ state since it is difficult to determine if the
the module output is transitioning or if it is in HiZ mode.

Best Regards,

Sheldon

Title: Re: Tristate output of Analog value
Post by sand_dolphin2 on Sep 27^th, 2010, 1:54am

sheldon wrote on Sep 27^th, 2010, 1:26am:

Sand Dolphin,

It appears that your module always outputs a 5V
If the V(Din) [rising edge]> 0.7 --> V( A5vout) = 5
If the V(Din) [falling edge] < 0.7 --> V( A5vout) = 5
since V(Din) > 0.1

....
Sheldon

thx Sheldon,

i wana make correction only one point.

Din is Digital signal.
And we define L2E on other system 1.5v(D1),0v(D0) on tran 0ns.
thus, when Din goes to high, V(Din) reached 1.5v and
Din goes to low, V(Din) reached 0v A.S.A.P.

this function model works fine now.

so how 2 add function Hiz-State by Analog solver(Verilog-AMS) ?

how about bellow way ?

I can make enable logic signal for driving or not. as ENABLE is set.

analog begin
@(cross(V(Din)-0.7,0));
if((V(Din)>0.1) & ENABLE ) temp = 1;
else if( ENABLE ) temp=0;

V(A5vout) <+ 5*transition(temp,0,1n,1n);

end

:(

i know , i should try myself at first.
but i can't. cos i'm not so familiar w/t Analog tool Environment.

now , i'm making test bench on Analog tool Environment.

plz give me kindly help and advice.