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Design Languages >> Verilog-AMS >> how to flush out the buffer in verilog A?
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Message started by Irvin73 on Sep 27^th, 2010, 10:19am

Title: how to flush out the buffer in verilog A?
Post by Irvin73 on Sep 27^th, 2010, 10:19am

Hi,
I run relatively long transient spectre simulation with some verilog-A block which on each "cycle" of simulation should print data to the log file. Like in following example -

Code:

@(cross(V(CNT_RST)-vth, +1)) begin
// ... some code here
$fwrite(logFile,"%d\t%.2f\t%.2f\t%.2f\n", row_index, cds_code,reset_code,signal_code)

end

The problem is that the log file updated only after the simulation completes, and I want to do monitoring of the log during the simulation. I think there is some way to control the flushing of the buffer, can anyone help with this?

Tnanks.

Title: Re: how to flush out the buffer in verilog A?
Post by Geoffrey_Coram on Sep 28^th, 2010, 6:04am

Try
$fflush(logFile);

Title: Re: how to flush out the buffer in verilog A?
Post by Irvin73 on Sep 28^th, 2010, 6:36am

It works, many thanks!

Interesting thing - this function is not documented, at least I can't find it in "Cadence®Verilog®-A Language Reference" pdf (2006). Is my documentation obsolete? :)

Thanks again for quick and useful response.

Title: Re: how to flush out the buffer in verilog A?
Post by Geoffrey_Coram on Sep 29^th, 2010, 8:45am

I found this in the IEEE 1800-2009 standard.

I know some vendors implement features like this in their (digital) Verilog simulators, and then I guess it's an easy port to add to their analog or AMS simulators.