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Design Languages >> Verilog-AMS >> Controlling Verilog-A Module Parameters Externally
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Message started by omar on Sep 29^th, 2010, 11:20am

Title: Controlling Verilog-A Module Parameters Externally
Post by omar on Sep 29^th, 2010, 11:20am

Hello,

I'm working with verilog-a compact models in spectre. I am wondering if there is a way to create a module such that I can change parameters in the module without opening the code. For example, when we're working with the compact model of a transistor, it would be really helpful to change the width in each simulation without having to open the verilog-a code each time.

Thanks

Title: Re: Controlling Verilog-A Module Parameters Externally
Post by Amit_Analog on Sep 29^th, 2010, 11:19pm

Hi,

I think this one can be done. Edit the CDF from icfb for the symbol cell view you want to use. Add the parameters you want to parametrize.

This may be helpful:
http://www-scf.usc.edu/~ee577/cadence_tutorial4.html

Title: Re: Controlling Verilog-A Module Parameters Externally
Post by Geoffrey_Coram on Sep 30^th, 2010, 6:27am

Amit's suggestion is good, if you're using icfb. If you're not, you need to tell us how you generate the spectre netlist.

Title: Re: Controlling Verilog-A Module Parameters Externally
Post by omar on Oct 1^st, 2010, 12:24pm

Thanks for the suggestions.

Amit's approach seems to work. I'm using icfb to get the netlists.