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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> for checking I/O behavior https://designers-guide.org/forum/YaBB.pl?num=1286242893 Message started by sand_dolphin2 on Oct 4th, 2010, 6:41pm |
Title: for checking I/O behavior Post by sand_dolphin2 on Oct 4th, 2010, 6:41pm Now , DUT has I/O (bi-directional) port w/t pull up or pull down resister. So, i wana check this function of this I/O. plz refer to my appended file to show testbench. -JTAG task(verilog-D) -LevelShifter( up to I/O voltage ) -DUT for checking behavior of these I/O , at first i make module on VAMS. //------------------------------------------ module LS_ams( Ain , A5vout ); input Ain; output A5vout; electrical Ain,A5vout; real temp; analog begin @(cross(V(Ain)-0.7,0)); if(V(Ain)>0.1) temp = 1; else temp=0; V(A5vout) <+ 5*transition(temp,0,1n,1n); end endmodule //------------------------------------------ about this, so many questions i have... at first, i want 2 know 2 question as first step. 1) Hiz case How does connect function works when JTAG task(verilog-D) drive Hiz? Does connect function which tool insert automatically translate Hiz directly ? now it seems so( trans Hiz ) on my simulation results. my understanding is correct? 2) output impedance how should i care for output impedance of this vams module. now it seems so low impedance on my simulation. cos, i can't fond pull up function of I/O. plz let me know... :'( |
Title: Re: for checking I/O behavior Post by sand_dolphin2 on Oct 7th, 2010, 1:13am Now, just i use Cadence's connect module. like as //--------------------------------- always @(Din) begin case(Din) 1'b0: begin Vstate=0; Rout=200; end 1'b1: begin Vstate=5; Rout=200; end 1'bz: begin Rout=10M; end // default: begin Vstate=vx; Rout=rx; end endcase end analog begin rout = transition(Rout,0,1n,1n,); // rout shifts linearly also; I(Avout) <+ (V(Avout)-transition(Vstate,0,1n,1n,))/rout; end //--------------------------------- it works well for translate Logic Hiz state to Analog solver. thx all. ;) |
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