The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> bind Error w/t System Verilog Assertion to AMS
https://designers-guide.org/forum/YaBB.pl?num=1286443098

Message started by sand_dolphin2 on Oct 7^th, 2010, 2:18am

Title: bind Error w/t System Verilog Assertion to AMS
Post by sand_dolphin2 on Oct 7^th, 2010, 2:18am

Now , i'm using Cadence's AMS Designer.

DUT was made by schema.
Modules of Test bench were made by Verilog-D or AMS.
TOP block of Test bench was made by schema.

So, i try to add System Verilog Assersion to Test Bench.

And so, i have one problem which are depending on
w/ or w/o bind function on System Verilog.

1) making System Verilog code w/o bind
No Error on compiling and runs well that assersion

like this

property pr_001; @(posedge TESTBENCHTOP.I13.a)
!TESTBENCHTOP.I13.b |=> TESTBENCHTOP.I11.D8out == 8'h00 ;
endproperty

2) making Sytem Verilog code w/t bind
Error occured on compilation

like this bind function of System Verilog

bind TESTBENCHTOP sva_monitor sva_monitor(
.CLK(I13.a),
.RST_X(I13.b),
.DOUT(I11.c)
);

anybody, plz let me know how to the best way for..

:(

Title: Re: bind Error w/t System Verilog Assertion to AMS
Post by sand_dolphin2 on Oct 12^th, 2010, 11:02pm

Cadence Japan let me know
there is possibility this caused by tool's bug.

for avoid this problem, Cadence japan advice bellow 2 cases

1) order reading sva,vams
not reading bind function before vams

2) on sva file
should be write bind first,
before module function which include assertions

easy way is 2),
Now i success for using SVA bind function on AMS Designer

anyway i'll let u know correct report from Cadence R&D

thx

;)