The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> Error running Cadence ams(spectre) using actual VHDL netlist
https://designers-guide.org/forum/YaBB.pl?num=1286505235

Message started by richloo on Oct 7^th, 2010, 7:33pm

Title: Error running Cadence ams(spectre) using actual VHDL netlist
Post by richloo on Oct 7^th, 2010, 7:33pm

1) by using "OSS-based netlister with irun"
ERROR: Missing .cdb or .oa file in library c090_phy_lib cell c090_bias view
bhv.
The OSS netlister requires a .cdb or .oa file in lib/cell/view
directory.
If one does not exist, you can create one either by importing the
text file using Verilog In or VHDL IN, or by opening and writing the file in the
Library Manager.

Question: How can I generate .cdb or .oa with VHDL behavioral code? I already have (master.tag pc.db prop.xx vhdl.vhms) in that compilation directory.

2) by using "cellview-based netlister with ncvlog,ncelab,ncsim"
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
ncelab: *W,DLWNEW: Intermediate file entity C090_PHY_LIB.C090_BIAS (AST)
is newer than expected by architecture C090_PHY_LIB.C090_BIAS:BHV (AST)
actual: Fri Oct 8 09:37:06 2010
expected: Wed Oct 6 10:08:14 2010.
.vdd_c( net25 ), .c_atb1( net19 ), .c_atb0( net14 ), .c_atb3(
|
ncelab: *E,CFMPTC (./ihnl/test/tb_c090_bias_dc/schematic/verilog.vams,25|14): VHDL port C090_BIAS.VSSC1 (/user/r1/temp/C_PHY/02/compiled/nccoex/c090_phy_lib/c090_bias/entity/vhdl.vhms: line 56, position 12) type is not compatible with Verilog.

Question: Is there limitation on VHDL in ams simulation? How to solve it?

Thanks in advance

Title: Re: Error running Cadence ams(spectre) using actual VHDL netlist
Post by jerome_ams on Oct 26^th, 2010, 8:37am

hi,

to your question 2)
I seems rather than your "vdd_c" port type is not supported by the netlister.

=> the Cadence netlister writes Verilog(ams) and you have to ensure that any signal/port at the interface of your vhdl(ams) model can be mapped to verilog(ams).
What is the type of "vdd_c"? Is it a real quantity?

Cheers,
Jerome