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Design >> Analog Design >> Poly Orientation
https://designers-guide.org/forum/YaBB.pl?num=1286511079

Message started by casual on Oct 7^th, 2010, 9:11pm

Title: Poly Orientation
Post by casual on Oct 7^th, 2010, 9:11pm

Poly orientation can affect the chip yield.

What is the recommended poly orientation should be set in some PDK? Horizontal or vertical?

At what technology, the poly orientation comes into great influence? I was told that 0.18um did not care about the poly orientation. Is it true?

Title: Re: Poly Orientation
Post by raja.cedt on Oct 7^th, 2010, 10:26pm

hi,
i don't think poly orientation will effect yield much, because with different poly orientations mainly effects while etching either width or length will change this may come as input refereed offset in comparators and like that. But what generally yield mean chip should work. More or less around .18u tech it doesn't matter.

Thanks.

Title: Re: Poly Orientation
Post by casual on Oct 10^th, 2010, 6:11pm

the Yield is reduced if the circuit performances are degraded, especially in big SOC system.

So, is 0.18um technology fine with any poly orientation..?
I think it is good practice to keep into one poly orientation if possible.

How about other technology, like 90nm? what technology starts to pay attention to poly orientation? welcome any commend

Title: Re: Poly Orientation
Post by love_analog on Oct 11^th, 2010, 6:07am

Poly width is a critical dimension (CD) In very fine ~40nm and below the tooling requires you keep poly in the same direction throughout the IC. This ensures you get the same repeatable results in high volume manufacturing.

Title: Re: Poly Orientation
Post by thechopper on Oct 12^th, 2010, 5:24pm

Poly-silicon is an amorfous material and as such the orientation is less relevant in setting a sheet rho value compared to an epi resistor for example. From that perspective the orientation is then not important.
It becomes important if you are looking for good matched resistors: regardless what orientation you choose you will have to lay out them with the same direction. That way geometrical errors - and not the sheet rho variation - will be minimized between those you want to match.

Best
Tosei

Title: Re: Poly Orientation
Post by vivkr on Oct 13^th, 2010, 4:43am

supermoment wrote on Oct 7^th, 2010, 9:11pm:

Poly orientation can affect the chip yield.

What is the recommended poly orientation should be set in some PDK? Horizontal or vertical?

Horizontal or vertical orientation is a matter of perspective. If I were to turn the wafer by 90 degrees, this definition would change. As emphasized by the others, you need to keep poly orientation the same in most of the advanced processes so that the transistors show similar behavior.

The primary reason is lithographic constraints, which require poly structures to be aligned in direction and repeat at a certain pitch in order to be able to form the gates correctly. This is of course mainly a constraint for the transistors with the narrowest channel lengths. So if you have several different kinds of devices available such as higher-voltage devices which were basically ported from older processes, then the above constraints may not apply.

I don't believe that a fixed orientation requirement existed in 0.18 um or even in 0.13 um if I recall correctly. Just check for the technologies where the gate length becomes smaller than the wavelength of light used in the lithographic process. I would guess that the constraint would start to appear around there.

That being said, you always want the same alignment for matching structures, and secondly, the term "poly" does not refer to polysilicon in some of the most modern processes which employ metal gates as there is no amorphous poly-Si being formed there. The term "poly" is simply a relic from the past and used for convenience as people are used to referring to the gate layer as poly. It's like using the term MOSFET for all FETs in the older technologies. There was no metal gate except in the very very first MOS technologies, but poly, but we keep using the term MOSFET. Now, we have MOSFETs again....

Vivek

Title: Re: Poly Orientation
Post by casual on Oct 13^th, 2010, 6:04am

Vivkr,
it is a good explanation.
when I was working in a MNC, the designers got to follow poly orientation strictly in IOring region, the reason is to have good predicted transistor performance to improve yield (SOC system). Anyway I think it is a good practice if possible.

Now in IBM 65nm, the transistor PDK setting got vertical/horinzontal setting. I just wonder how should I set it.

Title: Re: Poly Orientation
Post by vivkr on Oct 14^th, 2010, 5:24am

supermoment wrote on Oct 13^th, 2010, 6:04am:

Vivkr,

Now in IBM 65nm, the transistor PDK setting got vertical/horinzontal setting. I just wonder how should I set it.

Phew! no idea. I would just wonder how one could define an absolute vertical/horizontal orientation at all. Makes little sense to me. There has got to be a reference to something, maybe M1 or something like that. Ask your foundry rep.

Vivek

Title: Re: Poly Orientation
Post by Frank Wiedmann on Oct 14^th, 2010, 5:43am

Wafers do have an absolute orientation, see http://en.wikipedia.org/wiki/Wafer_(electronics)#Wafer_flats_and_orientation_notches.