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Design >> RF Design >> 2.4 GHz MSK transmitter
https://designers-guide.org/forum/YaBB.pl?num=1286765375

Message started by aaron_do on Oct 10^th, 2010, 7:49pm

Title: 2.4 GHz MSK transmitter
Post by aaron_do on Oct 10^th, 2010, 7:49pm

Hi all,

I've just started looking into MSK transmitter design, and I've noticed a popular architecture is to use direct VCO modulation at 2.4 GHz followed by a PA. This seems to require a rather complex PLL architecture for closed loop VCO modulation. I was wondering, why not do the modulation on a low-frequency VCO (1 MHz for example), and then upconvert the MSK signal and amplify it? That way the PLL architecture can be simpler. It also somewhat decouples the PLL design from the TX design. It seems the big issue is how to generate a sine wave at low frequencies...

Any thoughts are welcome.

thanks,
Aaron

Title: Re: 2.4 GHz MSK transmitter
Post by aaron_do on Oct 10^th, 2010, 11:37pm

Hi,

thanks for the reply. Just for the record, I mean to generate sin(ωt)and ±cos(ωt) and upconvert the IQ to RF rather than generate sin(ωt +ω_IFt) and upconvert it. What kind of image-rejection do you think is possible? I have not touched on transmitter design before, but based on the receiver deisgn i've studied, I suppose an image rejection of 30 dB is possible. Is this not true? For MSK, I think the SNR requirement for proper demodulation is probably around 10 dB, so 30 dB IRR should be sufficient. Please correct me if i'm wrong.

thanks,
Aaron

Title: Re: 2.4 GHz MSK transmitter
Post by aaron_do on Oct 11^th, 2010, 1:41am

Hi,

Quote:

Combination of Hilbert Transformation and Quadrature UpMixer.

I meant what level of image rejection is possible? i.e. 20 dB, 30 dB...

Quote:

Again you have to consider frequency separation between image and desired signal.

I don't really understand. If I want to transmit logic level 1, then the image frequency will be that of logic level 0. So logic 1 is 500 kHz, logic 0 is -500 kHz for example. They are the images of each other. So what kind of image rejection is required? Anyway perhaps I am missing something, so I will try out some simulations to see if I can understand it better.

thanks,
Aaron

Title: Re: 2.4 GHz MSK transmitter
Post by vp1953 on Oct 11^th, 2010, 3:46pm

Hi Aaron,

Quote:

What are the additional requirements for a PLL that uses direct VCO modulation that would not be needed for your scheme that you detailed above?

ps. you are quoting some replies but all i can see are your posts in this thread. Are you quoting from some other discussion?

Title: Re: 2.4 GHz MSK transmitter
Post by aaron_do on Oct 11^th, 2010, 6:31pm

Hi,

Quote:

What are the additional requirements for a PLL that uses direct VCO modulation that would not be needed for your scheme that you detailed above?

Well, I was refering to when you need to use closed-loop VCO modulation as opposed to open-loop VCO modulation. In a couple of the references I looked at, a fractional-N synthesizer was required to do closed-loop VCO modulation, while an integer-N synthesizer is sufficient otherwise.

Quote:

ps. you are quoting some replies but all i can see are your posts in this thread. Are you quoting from some other discussion?

Nope. For some reason pancho_hideboo's reply was removed. Seems like the same thing happened here:

http://www.designers-guide.org/Forum/YaBB.pl?num=1286704306

Basically he mentioned that the reason we use direct VCO modulation is because the image-rejection requirements are severe if you up-convert a low frequency MSK signal. Something like that anyway.

thanks,
Aaron

Title: Re: 2.4 GHz MSK transmitter
Post by vp1953 on Oct 12^th, 2010, 5:35pm

Hi Aaron,

Quote:

In a couple of the references I looked at, a fractional-N synthesizer was required to do closed-loop VCO modulation

What is your datarate? With your scheme, assuming a SNR of 20 db is required, all you need to have is 20 db of image rejection - is that the image rejection you are specifying for your design?

Title: Re: 2.4 GHz MSK transmitter
Post by aaron_do on Oct 12^th, 2010, 9:23pm

Hi vp1953,

at this point I haven't precisely defined the SNR requirement, but I assume that 20 dB is more than sufficient. The data rate is 250 kb/s, but the chip rate is 2 Mchips/s.

I also thought that the same image-rejection would suffice, but pancho_hideboo's original reply suggested that there might be something i'm missing. Currently I'm doing some ideal simulations using cadence to try and figure out if there are any problems.

thanks,
Aaron

Title: Re: 2.4 GHz MSK transmitter
Post by ACWWong on Oct 23^rd, 2010, 3:25pm

hi aaron,

just tried to read this topic... and am quite confused as its gets really cryptic when a load of the posts going missing....

anyway the most simple way to do this MSK transmitter (and what looks like you are talking about in your original post) is by an IQ modulator (SSB upconverter). The VCO in this case only need to be a CW LO signal (locked by standard PLL at the carrier freq), although you need a quadrature LO for the IQ modulator. The quadrature (hilbert transform) can be divide by 2 if the VCO is at 2*freqtx, or by polyphase filter or by quadrature VCO.
The baseband IQ representing your 2Mchip/s MSK can be generated by a digital modulator followed by a DAC to get the ±500kHz analog IQ signals.
The "image" rejection depends on your IQ phase and amplitude mismatches in both LO IQ path and baseband IQ paths... 20dB is pretty easy to meet though..
The quality of the transmission will be degraded by the finite "image rejection" and for that matter the carrier suppression (caused by DC offsets) and other spurious tones (due to crosstalk and non-linearity etc.) in the IQ modulator, but the limiting factor i think for the quality of the MSK transmission will be be noise of the final signal caused by PLL jitter (with additonal noise/error due to IQ modulator, PA, DAC etc.)

The MSK transmitter can be also be implemented using a loop modulator... i guess these are the architectures you are referring to when you say "direct VCO modulation". They use a fractional-N PLL in which the data modulation is applied to the feedback divider via a delta-sigma modulator, with the channel number. For PLL BW must be wide enough to follow the modulation, which causes a problem due to the PLL integrated noise will be high due to the wide BW. The get-out here is to use two-point modulation.... Anyway the advantage of the loop modulator techniques is that it can be lower power (no need for quadrature LO or IQ modulator), but is as you say its a bit more "complicated" as an architecture compared to standard IQ modulator approach.

cheers

aw