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Design Languages >> Verilog-AMS >> global nodes in verilog-ams
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Message started by Luke Whitaker on Oct 13^th, 2010, 6:26am

Title: global nodes in verilog-ams
Post by Luke Whitaker on Oct 13^th, 2010, 6:26am

Hello design community,

The cell I'm trying to make a verilog-ams module for has several global power nodes. There is a power on reset in the module that needs to monitor a global power signal. The top level schematic declares this node with an exclaimation point, vdd! for example. The global signal's ramp rate is controlled by a vpwl, so the global cannot be a static real value. How do I access these global power nodes from my verilog-ams module?

In general I don't like global variables (other than ground '0'), but the designer I'm working with does and wants to keep them in his design.

Thanks for your help.

Best regards,

Luke

Title: Re: global nodes in verilog-ams
Post by Marq Kole on Nov 17^th, 2010, 7:01am

The global node has to be defined somewhere. One way to do this is to create a separate module at top-level - say "module globals ();" - that contains these top-level nodes and then reference them from the AMS by using their hierarchical names:

Code:

`include "disciplines.vams"

module globals ();

electrical \vdd! ; // escaped identifier so make sure whereever you use it there is whitespace following it.

endmodule

module some_design_block ( ... );

...

analog begin

@(above(V(globals.\vdd! ) - thresh_hi))
...

end

endmodule

You might run into trouble using the escaped identifier - in that case make a connection from vdd! to a global node with a name that doesn't require an escaped identifier.

Cheers,
Marq