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Design >> Analog Design >> cascoode biasing circuit
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Message started by ontheverge on Oct 14^th, 2010, 5:25am

Title: cascoode biasing circuit
Post by ontheverge on Oct 14^th, 2010, 5:25am

Hi,
I'm designing a biasing circuit for folded cascode op-amp, the designed circut structure is shown below: there are still a few things i'm not quite clear:

1. are M14, M15 always necessary?
2. how to characterize the performance of a biasing circuit?
3. in what way does the gain of M1, M2(gm1*ro1*gm2*ro2), or M8,M9 affects the overall biasing circuit's performance?

thanks,
Steve

Title: Re: cascoode biasing circuit
Post by Alexandar on Oct 14^th, 2010, 5:41am

1. They reduce mismatch of current due to otherwise different drain voltages.
2. Check if all transistors stay in saturation with PVT
3. Parameters as noise and impedance can influence the performance of the circuit.

Title: Re: cascoode biasing circuit
Post by RobG on Oct 14^th, 2010, 8:35am

Lex wrote on Oct 14^th, 2010, 5:41am:

1. They reduce mismatch of current due to otherwise different drain voltages.

Just to clarify/expand a bit.

M12-13 could have very different drain voltages from M1 unless the cascode is used. Also, the power supply rejection of the M1/M12/M13 mirror will be poor if the channel lengths are short. You could get similar performance without the cascode by making the the channels longer at a cost of more cap on the drain and slower response of the M1 mirror.

For verification, I like to make sure Vds > Vdsat+100mV over all corners. Preferably 150mV greater.

The "bottom" device of a mirror should have gm as small as possible (usually limited by bandwidth)to minimize noise and mismatch caused by Vt mismatches. On the other hard, the cascode device should have as large of gm as possible to increase gm*ro and minimize the pole due to the impedance looking into that node.

rg

Title: Re: cascoode biasing circuit
Post by ontheverge on Oct 14^th, 2010, 6:45pm

As far as output swing is concerned, want Vb2 low (Vb3 high), however, if Vov2 is not minimized, reducing Vb2 will reduce Vds1, hurt intrinsic gain from M1, so I figure maybe I should minimize Vov2 by increase its Width, is that the right way to work on it?

Title: Re: cascoode biasing circuit
Post by RobG on Oct 14^th, 2010, 7:33pm

ontheverge wrote on Oct 14^th, 2010, 6:45pm:

so I figure maybe I should minimize Vov2 by increase its Width, is that the right way to work on it?

... or shortening the length. Both of these increase gm.

rg