The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> Spectre-Verilog simulation problem https://designers-guide.org/forum/YaBB.pl?num=1287111592 Message started by Daniel Lai on Oct 14th, 2010, 7:59pm

Title: Spectre-Verilog simulation problem Post by Daniel Lai on Oct 14th, 2010, 7:59pm Hi all, Thanks for your attention. I have a problem about spectre-verilog simulation in a hierarchical circuit. This hierarchy includes schematic (MOS,R,L,C), verilog-A RTL, and verilog RTL, which is shown in attached figure 1. The top cell is created by hierarchy editor as a config view, and set up the mix-signal partition and interface correctly. The problem is when I correctly set the input of Vin (pulse signal), Clock (pulse signal), and register input (logic high/low), the verilog RTL output is always zero. This is found that the verilog code were not operated correctly by input signal, and was debugged by following way, which is shown in figure 2. We descend the top cell and disconnect the input signal to verilog, and create the same source inside the top cell for verilog. Then the verilog output is correct this time. Does anyone know if there is any limitation in spectre-verilog simulation about hierarchy, please kindly advice me, thanks. Daniel

Title: Re: Spectre-Verilog simulation problem Post by Daniel Lai on Oct 21st, 2010, 7:14pm This problem was found the interface of mixed signal was not setup correctly at top level. The mixed signal interface of a hierarchical architecture should be set up at all of analog-digital interface.

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