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Design Languages >> Verilog-AMS >> 288 bit SIPO register
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Message started by Prashant Babu on Oct 20^th, 2010, 2:21am

Title: 288 bit SIPO register
Post by Prashant Babu on Oct 20^th, 2010, 2:21am

Hi,

Can anybody please tell me how to write a Verilog-A code for a 288 bit SIPO register.
Since the number of bits are quite large, I tried to use "for" loop statements for assigning values and also in the transition statement, but have been getting a lot of errors.
Any help will be appreciated.

Thanks,
Prashant

Title: Re: 288 bit SIPO register
Post by Prashant Babu on Oct 20^th, 2010, 6:40am

I tried the following code:

`define BITS_IN_REG 288

module SIPOREG_288BIT(vin_d, vout_d, vclk);

output [`BITS_IN_REG-1:0] vout_d;

electrical vin_d;
electrical [`BITS_IN_REG-1:0] vout_d;
electrical vclk;

parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans = 2.5;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);

integer d[0:`BITS_IN_REG-1];

integer bit_num;

analog begin

//
// roll the register and load the new input bit
//
@ (cross( V(vclk) - vtrans, +1, 1.0, vclk.potential.abstol) ) begin
for (bit_num = (`BITS_IN_REG-1); bit_num > 0; bit_num = bit_num-1)
d[bit_num] = d[bit_num-1];
d[0] = V(vin_d) > vtrans;

generate i (0,(`BITS_IN_REG-1)) begin
V(vout_d[i]) <+ transition((d[i] ? vlogic_high : vlogic_low), tdel,trise,tfall);
end

end

end

`undef BITS_IN_REG

endmodule

However, the problem is that the outputs are generated only after all the data have been shifted.

How can I shift as well as generate the output at the same time?
For example, I want the output vout_d[0:277] at each bit shift.
I cant use the "generate" statement within the @cross because it gives me an error.
Anybody out there who can help me out with this?