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Modeling >> Behavioral Models >> A high side non-ideal current mirror in Verilog-A?
https://designers-guide.org/forum/YaBB.pl?num=1287660069

Message started by the_wavefunction on Oct 21^st, 2010, 4:21am

Title: A high side non-ideal current mirror in Verilog-A?
Post by the_wavefunction on Oct 21^st, 2010, 4:21am

Hi,

One of my circuits in Cadence needed a high performance pmos current mirror and I decided to simulate it initially using Verilog-A.

Essentially, my idea of the mirror circuit was to implement two simple resistive branches with one being the probe and the other, the source. It was also vital that in addition to the mirrored current, the voltage at the output terminal track the input terminal voltage as well.

However, according to simulations, when the current is mirrored properly, the terminal voltage is not and vice versa.
I do realize that in Verilog-A, a branch cannot be both a flow and potential source simultaneously!

So, after numerous revisions the present version of my code looks like this:
-----------------------------------------------------------------
`include "constants.vams"
`include "disciplines.vams"

module curr_mirr(srcA, srcB, mrrA, mrrB);

input srcA,srcB; // source branch
inout mrrA; // mrrA, srcA are tied to Vdd externally
output mrrB; // mrrA, mrrB - mirror branch

electrical srcA, srcB, mrrA, mrrB;
electrical int; // node joining current source and Rmodel

real Rmodel;

analog begin
@(initial_step) begin
Rmodel = 10K;
end

Rmodel = 10K;

V(srcA,srcB) <+ I(srcA,srcB) * Rmodel;
I(mrrA,int) <+ I(srcA,srcB);
V(int,mrrB) <+ I(int,mrrB) * Rmodel;

end

endmodule
-----------------------------------------------------------

A simulation of this code tracks the current, but not the terminal voltage.
In other words: V(srcB) ≠ V(mrrB), which is against the desired result.

Any suggestions or opinions on this are utmost welcome!

Title: Re: A high side non-ideal current mirror in Verilog-A?
Post by jerome_ams on Oct 26^th, 2010, 8:04am

Hi,
Here my first-guess suggestion: could the use of Verilog-AMS, rather than Verilog-A, be an option for you?

Using Verilog-AMS, the modeling will be quite staight forward (voltage-current duality supported)

Hope it helps,
Jerome

Title: Re: A high side non-ideal current mirror in Verilog-A?
Post by the_wavefunction on Oct 27^th, 2010, 12:53am

Hi Jerome,

Good to know from you that it can be effected in Verilog-AMS.

But I found out that I can't avail myself of Verilog-AMS here!

Title: Re: A high side non-ideal current mirror in Verilog-A?
Post by jerome_ams on Oct 27^th, 2010, 1:46am

Sorry, I have to reconsider my answer. At the first glance I have just picked up this sentence:

Quote:

I do realize that in Verilog-A, a branch cannot be both a flow and potential source simultaneously

and was reacting on it. But I misread your point.

VerilogA DOES allow you to describe the voltage-current duality. VerilogAMS will just allow you on top of that to describe digital discrete events.
(VerilogAMS can basically be seen as the merger of VerilogA and Verilog-HDL).

Let me come back to you in another post and try to adress your question more effectively

Title: Re: A high side non-ideal current mirror in Verilog-A?
Post by Ken Kundert on Oct 27^th, 2010, 2:01am

A current mirror should only set its output current. The output voltage will be determined by the load.

-Ken

Title: Re: A high side non-ideal current mirror in Verilog-A?
Post by jerome_ams on Oct 27^th, 2010, 2:32am

hi again,

I agree with Ken.

The way we usually implement a current mirror model is the following:
1) the current flowing in the sink branch (a resistor) is monitored. It is the target current
2) this target current might be multiplied by a gain factor and then passed as a parameter to a current source. The current source is usually described as a "real" one, meaning its voltage drop (Vdrop) between positive and negative nodes is checked. If it drops below a certain value, the current source reduces its current (sufficient voltage should be there to allow full current to flow)

=> the potential at the output node of the current source is determined by the load connected to the current source, not by the voltage on the sink branch

Cheers,
Jerome

Title: Re: A high side non-ideal current mirror in Verilog-A?
Post by the_wavefunction on Oct 27^th, 2010, 9:05am

Hi Ken & Jerome,

Thanks to your comments, I now modified the inputs of the subsequent stage (which is actually a Verilog-A transimp amplifier) to suit the desired operating levels.

I was initially thinking only on the lines of advanced cascoded current mirrors, where generally the Vds matching of both mosfets are sought after, and I told myself that there has to be some model to mimic that. But I missed the point that, there as well the drain voltage at the cascoded output changes anyway!

Thanks once again for pulling me on the right track :)