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Design >> Analog Design >> CMOS current reference schemes
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Message started by AnalogDE on Oct 25^th, 2010, 11:41am

Title: CMOS current reference schemes
Post by AnalogDE on Oct 25^th, 2010, 11:41am

I'm doing some research on current reference schemes. I've seen the following two schemes: Both utilize a BGR/VREF to generate a gate bias

1. NMOS biased at ZTC (zero-tempco point), where mobility and vth variation cancel each other.

2. NMOS in series with opposite tempco resistor -- NMOS has positive tempco resistance balanced with negative tempco resistor.

What are the pros/cons of the two schemes? Any pointers to references/papers appreciated.