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Simulators >> Circuit Simulators >> SAR ADC Hold time simulation....
https://designers-guide.org/forum/YaBB.pl?num=1288258839

Message started by somisetty on Oct 28^th, 2010, 2:40am

Title: SAR ADC Hold time simulation....
Post by somisetty on Oct 28^th, 2010, 2:40am

Hi all,

can any one help me with "how to perform hold time simulation in SAR ADC?

Thanks

Title: Re: SAR ADC Hold time simulation....
Post by sheldon on Oct 29^th, 2010, 6:19pm

Somisetty,

It would help if you provide more information when you asked a
question since the details of your design impact the response. For
example, do you have an external Sample and Hold or are you using
the Capacitor DAC to sample the input? The general procedure for
analyzing noise in switched capacitor circuits is covered in,

http://www.designers-guide.org/analysis/sc-filters.pdf

Best Regards,

Sheldon

Note: I know that in general a SARADC does not require an external
Sample and Hold, however, parallel SARADC should have one.