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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> two stg OTA https://designers-guide.org/forum/YaBB.pl?num=1288601237 Message started by ontheverge on Nov 1st, 2010, 1:47am |
Title: two stg OTA Post by ontheverge on Nov 1st, 2010, 1:47am Hi, I noticed that in miller-compensated two stage OTA, if the first stage is PMOS driven, the output stg is NMOS and vice versa, is there a special reason for that? thanks, Steve |
Title: Re: two stg OTA Post by raja.cedt on Nov 1st, 2010, 2:09am hi, 1.common mode voltage of the 1st stage o/p can easily drive 2nd stage with out any level shifting. 2.Supply rejection will be good. Thanks. |
Title: Re: two stg OTA Post by ontheverge on Nov 1st, 2010, 5:39pm Hi Raja, thanks for the reply, can u elaborate a little bit on supply rejection? thanks, Steve |
Title: Re: two stg OTA Post by raja.cedt on Nov 1st, 2010, 7:58pm hi, Assume you have nmos input diff pair in the first stage and pmos input 2nd stage, so due to pmos diode connected load at the first stage entire supply noise will come to output, so if 2nd stage is pmos then pmos gate will change by same amount of supply noise and at the same time source will be changed by same amount due to VDD connection. hence you would not see any change in 2nd stage output. Thanks. |
Title: Re: two stg OTA Post by aamar on Nov 2nd, 2010, 9:40am There are other two advantages which are 1. for the highest gain of the second stage, the vin (common mode as raja mentioned) for the second stage input transistor should be biased near the vth or vdd-vth in case of nmos and pmos respectively, which is then best implemented using the opposite type transistor from that used in the input differential pair. 2. The load of the second stage is a mirror from the tail current of the first stage and therefore no need for an additional bias voltage. Best regards, aamar |
Title: Re: two stg OTA Post by thechopper on Nov 15th, 2010, 6:28pm one advantage more... the second stage being the same type of the first stage active load allows for perfect balance of voltages if properly sized, thus systematic input referred offset can be minimized Best Tosei |
Title: Re: two stg OTA Post by raja.cedt on Nov 15th, 2010, 8:31pm hi chopper, if i am correct you are talking about sharing bias between both stages rite.... Thanks. |
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