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Simulators >> AMS Simulators >> Building TOP design by Verilog-AMS
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Message started by sand_dolphin2 on Nov 1^st, 2010, 4:15pm

Title: Building TOP design by Verilog-AMS
Post by sand_dolphin2 on Nov 1^st, 2010, 4:15pm

Hi there!

I want to build TOP design by not schematics but Verilog-AMS

So now i consider trying to make TOP
which connect these blocks
-PADs
-some Analog blocks are made by schematics
-Logic block(RTL)

by not schema but Verilog-AMS.

in this case
i wonder that, analog block(schematic) will be trans to net list by simulator
then i can't debug signal behavior on Analog blocks.

i want to trace behavior of signals under Analog blocks
like bellow attached view.

please let me know.
at first, can or can not

Now i use cadence's AMS Designer(solver APS)

i believe
this way will reduce time to build top design compared w/t schematic.

And , we can use Logic layout tool (like as Synopsys ICC) directly
after changing definition from electrical to wire...

Title: Re: Building TOP design by Verilog-AMS
Post by Geoffrey_Coram on Nov 4^th, 2010, 5:54am

sand_dolphin2 wrote on Nov 1^st, 2010, 4:15pm:

i wonder that, analog block(schematic) will be trans to net list by simulator

I don't know what "trans" means -- transparent? translated?

I know Verilog-AMS allows you to instantiate Spice primitives; I suppose it's simulator-specific how you instantiate subcircuits, and how the simulator finds the subckt definitions, model libraries, etc.

I would expect, though, that if you simulate it with APS, then somewhere inside APS are those transistors, and it should be possible to "see" the waveforms.

Title: Re: Building TOP design by Verilog-AMS
Post by sheldon on Nov 5^th, 2010, 3:34am

Sand Dolphin,

Your post was not very clear but it seems that you may have
confused using schematics with using schematics of transistor level
designs. Certainly using transistor level schematics is not top down
design. However, using schematics can be the basis for top down
design. You might want to review the example at the following link,
it is a paper by Jonathan David. In the paper, he uses a schematic
based approach to design from top-level to block level. He creates
three levels of models as he refines the design. The models are
parameterized so that you can trade-off block performance for
system performance.

http://ewh.ieee.org/r6/scv/cas/archives/2004David.pdf

Please review the paper, it will help you understand how schematics
and Verilog-AMS may be used for top-down design.

Best Regards,

Sheldon

Title: Re: Building TOP design by Verilog-AMS
Post by sand_dolphin2 on Nov 7^th, 2010, 4:24pm

Geoffrey_Coram wrote on Nov 4^th, 2010, 5:54am:

I don't know what "trans" means -- transparent? translated?

@Geoffrey_Coram
　thx for your correction. that means "translated".

sheldon wrote on Nov 5^th, 2010, 3:34am:

@sheldon
　thx for your good advice and letting me Candence's info...
　and i know the better way to use verilog-AMS.
　like as on page 4,5 of Cadence's pdf file which u linked.

So ,
　I want to make Turn around Time shorter
　to make TOP design and Test bench too
　not only easy simulate system level behavior and quality.

So , basically i want to consider bellow situation
In case of team was configured from
- many Analog engineers ( only know bottom up design flow )
　they can't make behavior models of their designs.
- some Digital engineer ( only know top level design flow )
- chip is not so big system, but routing signals of TOP are so many.
　
　and, Analog engineers are so busy
　to build transistor based design and lay out chip.
　then, they have no time to make top design on early stage
　and can't simulate as top level system.

Now
　we try to make Digital engineers help to
　build and lay out and simulate Top design which is made from
-some analog design macro's(are made by bottom up designer)
-and one Logic blocks(is made by top down desinger).

then, i make this thread to
　easily making TOP design and test benches
　and trying TOP lay out for Digital Engineers.

so i think,
　this thread do not care for top level or not as for making chip.

　cos analog macros are building by Analog engineers at starting stage...
　and thye can't build Analog macros by top down ....

So, in this case
　Is there No advantage for using verilog-AMS for top design ???

　plz feel free asking to me....

:'(

.

Title: Re: Building TOP design by Verilog-AMS
Post by jbdavid on Nov 11^th, 2010, 12:08am

for interconnection why wouldn't simple structural verilog be good enough ? easily manipulated by perl, and can be included in top level rtl if you need to do some synthesis, place and route for the design top.