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Design >> Analog Design >> second pole estimation
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Message started by ontheverge on Nov 5^th, 2010, 7:13am

Title: second pole estimation
Post by ontheverge on Nov 5^th, 2010, 7:13am

Hi,

if a single stage folded cascade OTA is used in switch capacitor circuit, the 2nd pole would be at the source of cascade stage (both PMOS and NMOS), to estimate this pole, i tried to use f=1/2*pi/(R*C), i figure the resistance is roughly 1/gm, however, the capacitance expression is messy, Cgs of cascade stage of course, but there are also bunch of cds and cgd, so how to include these parameters into design in a feasible way to satisfy target 2nd pole?

thanks,

Steve

Title: Re: second pole estimation
Post by raja.cedt on Nov 6^th, 2010, 11:20pm

hi,
your analysis is correct only but many times what will happen is the total impedance at the folding node is the parallel combination of bottom gm as well as top pmos gds. So its not uncommon to have higher gds because of more current through Top pmos. So please inclde that gds it may get you to correct position or please refre the follwoing pap (well design oriented pap).

Design procedures for a fully differential folded-cascode CMOS operational amplifier

Thanks.