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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> How to trace analog value as real value ? https://designers-guide.org/forum/YaBB.pl?num=1289292812 Message started by sand_dolphin2 on Nov 9th, 2010, 12:53am |
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Title: How to trace analog value as real value ? Post by sand_dolphin2 on Nov 9th, 2010, 12:53am Hi guys, Now, I want trace hierarchical analog value as real value. Hierarchical Nod name is TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc and the SUB_A_B block is made by schematic. I define real value as bellow in verilog ams module. real real_value_node_abc; real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc; but compile error occur on AMS Designer of Cadence. here is irun.err real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc; | ncvlog: *E,EXPLPA (aaa.vams,29|11): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)]. real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc; | ncvlog: *E,ILLHIN (aaa.vams,29|44): illegal location for a hierarchical name (TESTBENCH). real_value_node_abc = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc; | ncvlog: *E,EXPLPA (aaa.vams,29|52): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)]. module worklib.aaa:vams errors: 3, warnings: 0 please let me know how to refer analog value as real. :-/ btw: Sorry for confusing you in always my bad English. . |
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Title: Re: How to trace analog value as real value ? Post by Geoffrey_Coram on Nov 9th, 2010, 5:29am If the node were local to the module and declared as discipline electrical, you'd do: real_value_node_abc = V(node_abc); because V() is the access function for electrical. I'm not sure how this will work with the hierarchical node name, nor what discipline is assumed for that node. |
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Title: Re: How to trace analog value as real value ? Post by sand_dolphin2 on Nov 9th, 2010, 3:17pm Geoffrey_Coram wrote on Nov 9th, 2010, 5:29am:
@Geoffrey_Coram thx for your good advice, now i correct verilog ams code as your advice. But after correcting , still now Error occur ( error number were reduced from 3 to 1 ) i want to check analog value of nodes of schematics base design. here is irun.err file: aaa.vams real_value_node_abc = V(TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc); | ncvlog: *E,EXPLPA (aaa.vams,30|20): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)]. module worklib.aaa:vams errors: 1, warnings: 0 even though bellow code, same error occur electrical tempa = TESTBENCH.DUT.SUB_A.SUB_A_B.node_abc; real_value_node_abc = V(tempa); and proving to node which is made by verilog ams has same error too... What does this error message means ? i'm not sure this error comes from hierarchical node name... plz give me some advice... i'm waiting for your kind. :) |
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Title: Re: How to trace analog value as real value ? Post by Ken Kundert on Nov 9th, 2010, 5:58pm You've cut out too much. The error is in the code above the line you are showing. -Ken |
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Title: Re: How to trace analog value as real value ? Post by sand_dolphin2 on Nov 10th, 2010, 11:36pm i should correct, here is Verilog Ams code which occur error Quote:
and here is irun.error Quote:
when i comment out verilog ams code like this, do not occur this error. Quote:
i wonder 1)Mr Geoffrey_Coram's comments Quote:
2)one phrase of irun Error message Quote:
plz give me some kind.... . |
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Title: Re: How to trace analog value as real value ? Post by Ken Kundert on Nov 11th, 2010, 12:35am I think you need to put that code inside an analog block. You make it difficult to help you by only giving us a line or two at a time. It would be better to cut your example down as small as can be such that it still exhibits the problem and then give the whole example. It is sometimes hard to find problem if you can't examine the whole model. -Ken |
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Title: Re: How to trace analog value as real value ? Post by sand_dolphin2 on Nov 11th, 2010, 12:56am Dear kundert, Ken Kundert wrote on Nov 11th, 2010, 12:35am:
OK, I fully agree w/t u. I'll try to make sample code to make same error. DUT and TEST bench plz wait for moment..... :) |
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Title: Re: How to trace analog value as real value ? Post by sand_dolphin2 on Nov 11th, 2010, 5:54pm Ken Kundert wrote on Nov 11th, 2010, 12:35am:
word, i solved this problem! and this function work well.. any thx ... correct verilog ams code is here Quote:
next , i will add sample. ;) |
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Title: Re: How to trace analog value as real value ? Post by haykp on Nov 11th, 2010, 10:32pm Hi Sand_dolphin2, Please sorry for my out of context question, but I need your answer very much. So from your question I see that you are working with analog verilog or verilog ams. I am not very familiar with analog verilog, but I know pretty well the verilog digital one. So it is not clear for me why to use analog verilog, if we have spice or other analog simulators. Could you please expand why you use the analog verilog, why spice is not acceptable for your issue. My belief is that using mixed simulations you can always model the analog part with spice and digital part with verilog. |
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Title: Re: How to trace analog value as real value ? Post by sand_dolphin2 on Nov 12th, 2010, 12:02am NVM, and well come your question!! Because i'm digital engineer of verification and design. Then i'm so familiar w/t verilog-D than verilog-A same on u, we should go to verilog-AMS for Mixed signal simulation u know. My design include some analog parts which build by schema. I wana make test bench by verilog-AMS(text base) and check analog signals by system verilog vir conversion to Digital. as u know, real and wreal is good for this way. any other ? |
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