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Design Languages >> Verilog-AMS >> How to append data to a file instead of overwrite it in VerilogA?
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Message started by wandola on Nov 13^th, 2010, 6:45pm

Title: How to append data to a file instead of overwrite it in VerilogA?
Post by wandola on Nov 13^th, 2010, 6:45pm

I create a verilogA file to save some signals into a file during my simulation. It works.

Then I try to run Monte Carlo simulation. It turns out that everytime when a new run starts, my old data from previous run are all overwritten by the verilogA block. ('cause the file name is the same during monte carlo runs.)

So anybody knows how to append the data to a existing file? instead of overwrite it...

Thanks a lot. :-[

Title: Re: How to append data to a file instead of overwrite it in VerilogA?
Post by Geoffrey_Coram on Nov 15^th, 2010, 6:23am

Per the 1364-2005 (digital Verilog) LRM, the $fopen system function takes a second argument, which can be "a" to append.

Verilog-AMS should follow the same syntax, since it's based on that LRM.