The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> question about listing02-09+pll+ams
https://designers-guide.org/forum/YaBB.pl?num=1290043719

Message started by mustangyhz on Nov 17^th, 2010, 5:28pm

Title: question about listing02-09+pll+ams
Post by mustangyhz on Nov 17^th, 2010, 5:28pm

plltop:
vco #(.f0(1.5E9), .kvco(50.0E6), .rin(100k))

module vco (out, ps, ns);
parameter real f0 = 100k; parameter real kvco = 10k;
parameter real rin= 100k from (0:inf);
output out;
electrical ps, ns;
reg out;
logic out;
real vin;
initial out = 0;
always begin
vin = V(ps, ns);
# (0.5e9 / (f0 + kvco * vin))
out = ~out; end

analog I(ps, ns) <+ V(ps,ns)/rin;
endmodule

dose it mean:
1, f0=1.5E9
2, out = ~out after every (0.5e9 / (f0 + kvco * vin))
then the period of signal out is about 666ms, I think it should be 666ps. I delete 'e9' ,and I got the wrong answer.
why?

Title: Re: question about listing02-09+pll+ams
Post by mustangyhz on Nov 17^th, 2010, 5:49pm

I see,
timescale
for vco: 1ns/1ps
for plltop: 10p/1ps

Title: Re: question about listing02-09+pll+ams
Post by mustangyhz on Nov 17^th, 2010, 6:09pm

PLLTOP: timescale:10ps / 1ps
VCO: timescale:1ns / 1ps

in plltop:
capacitor #(.c(30n)) C (err, err2);
resistor #(.r(200)) R (err2, gnd);
vco #(.f0(1.5E9), .kvco(50.0E6), .rin(100k)) VCO (.ps(err), .ns(gnd), .out(out));
in vco:
parameter real f0 = 100k;
parameter real kvco = 10k;
parameter real rin= 100k from (0:inf);

question:
1, what does this mean?
capacitor #(.c(30n)) C (err, err2);
resistor #(.r(200)) R (err2, gnd);
2, it is different for fo,kvco,rin in plltop and vco. why? How dose this work?

Title: Re: question about listing02-09+pll+ams
Post by Geoffrey_Coram on Nov 18^th, 2010, 6:25am

mustangyhz wrote on Nov 17^th, 2010, 5:28pm:

dose it mean:
1, f0=1.5E9
2, out = ~out after every (0.5e9 / (f0 + kvco * vin))
then the period of signal out is about 666ms, I think it should be 666ps. I delete 'e9' ,and I got the wrong answer.
why?

1. Yes, the #(.f0(1.5E9)) is a parameter override.
2. I would expect vin near 0, or in any case, f0 + kvco*vin is approximately f0 (since kvco is 50E6 << 1.5E9). Thus, the assignment of out = ~out happens every 0.5E9/1.5E9 = 1/3 = 333ms, so the period is twice that.

Title: Re: question about listing02-09+pll+ams
Post by Geoffrey_Coram on Nov 18^th, 2010, 6:26am

mustangyhz wrote on Nov 17^th, 2010, 6:09pm:

1, what does this mean?
capacitor #(.c(30n)) C (err, err2);
resistor #(.r(200)) R (err2, gnd);

The first line is an instance of "capacitor" named "C", with its terminals connected to nodes "err" and "err2" and a value of 30n.
In SPICE:
C err err2 30n
Similarly, the second line would be
R err2 gnd 200

Title: Re: question about listing02-09+pll+ams
Post by mustangyhz on Nov 21^st, 2010, 12:32am

Geoffrey_Coram
thank your repling, I have several questions:
1、Do you think this capacitor(30nf) is too big!
2、I think there is only a capacitor for a second order PLL:
capacitor #(.c(350p)) C (err, gnd);
two capacitor and a resistor for a three order PLL：
capacitor #(.c(100p)) C (err, gnd);
capacitor #(.c(300p)) C (err, err2);
resistor #(.r(20k)) R (err2, gnd);
How did you select the value of these passive compenents？
3、1 ms is too long for a PLL simulation?
4、Is the voltage between err and gnd the control voltage of the VCO? It dose not change after 50us. Why？

Title: Re: question about listing02-09+pll+ams
Post by mustangyhz on Nov 23^rd, 2010, 5:08am

I have solved all these problems!

Title: Re: question about listing02-09+pll+ams
Post by mustangyhz on Nov 24^th, 2010, 4:13pm

simulation results_1:

Title: Re: question about listing02-09+pll+ams
Post by mustangyhz on Nov 24^th, 2010, 4:16pm

simulation results_2:
Dose anybody know why there is about 3 ns phase difference between fref and the feedback, the two input signal of the pfd?