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Design Languages >> Verilog-AMS >> programmable divider
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Message started by dsenderowicz on Nov 18^th, 2010, 3:09pm

Title: programmable divider
Post by dsenderowicz on Nov 18^th, 2010, 3:09pm

Hi,

I was wondering if there is any programmable divider implemented in veriloga that is free from hidden state variables to run PSS analysis. The example shown in Kundert's paper is for a fixed ratio.

Thanks.

Daniel