The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Different convergence of verilog-A sim between different versions of hspice
https://designers-guide.org/forum/YaBB.pl?num=1290294841

Message started by neoflash on Nov 20^th, 2010, 3:14pm

Title: Different convergence of verilog-A sim between different versions of hspice
Post by neoflash on Nov 20^th, 2010, 3:14pm

I'm having trouble with convergence in verilog-A simulations in HSPICE version 2010.03.

The simulation runs well in 2008.03 and 2009.09-SP1 release. However, seems to get stuck somewhere in the simulation and runs extremely slow at one single time point.

Any people have similar experience like this and would like to make some general suggestions?

I do have similar issue before when migrating to version 2009.09-SP1. However, that internal time step too small issue seem to be solved easily by replacing some direct voltage assignment with a transition filter.

Like this: v(a) <+a; --> v(a) <+ transition(a, td, tr);

This time, this kind of trick seems not impact the convergence. Thanks.