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Design >> Analog Design >> Low-voltage biasing network
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Message started by rfmagic on Nov 24^th, 2010, 7:23am

Title: Low-voltage biasing network
Post by rfmagic on Nov 24^th, 2010, 7:23am

Hi all,

I am designing an opamp in a low supply voltage process (vdd=1V). in order to get a feeling of the circuit I have designed a simple diff-pair with a tail current source. the main problem I am facing now is acheiving a good mirror to the current source as the Vds of the mirroring device and the current source are different and limmited due to the low headroom of the diff-pair. can anyone suggest a biasing network for low voltage current mirrors? of recommend a book discussing this topic?

Thanks

Title: Re: Low-voltage biasing network
Post by panditabupesh on Nov 24^th, 2010, 1:50pm

You could use stacked transistors like the traditional low voltage bias circuit. Connect the gate of top transistor to your expected input common mode voltage. The top transistor has size relation with diff transistors and the bottom one with the tail of diff pair.

Bupesh

Title: Re: Low-voltage biasing network
Post by rfmagic on Nov 28^th, 2010, 12:00am

Thanks,

IN fact my haedroom is so limited that I have tried to use stacked configuration but it is marginal across PVT. I finaly go a solution that might work in all conditions - - but im am still working on it.