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Design >> RF Design >> Kvco
https://designers-guide.org/forum/YaBB.pl?num=1290773769

Message started by raja.cedt on Nov 26^th, 2010, 4:16am

Title: Kvco
Post by raja.cedt on Nov 26^th, 2010, 4:16am

hi,
for DDR3 in 65nm i am designing one ring oscillator based PLL i have chosen mennetis delay cell based ring oscillator but its giving 7g Kvco. I tried many ways to reduce this but i am not able to go significantly below. So i just want to know for 1g to 1.8g range will this architecture gives lower Kvco? other can any one suggest some god architecture which gives less Kvco like 2 to 3G.

Thanks.