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Simulators >> Circuit Simulators >> One variable inside a verilog-A module not saved
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Message started by ywguo on Nov 29^th, 2010, 7:53pm

Title: One variable inside a verilog-A module not saved
Post by ywguo on Nov 29^th, 2010, 7:53pm

Hi Guys,

I tried to save the variables inside a verilog-A module. A part of the verilog-A code is listed below.

Code:

`define NUM_ADC_BITS 10
real unconverted;
real halfref;

real vd[0:`NUM_ADC_BITS-1];
integer i;

Then I chose Outputs --> Save All... --> Select AHDL Variables (saveahdlvars) --> All. I saw unconverted, halfref, and i in the results browser. However, there was no vd. I checked the netlist, it has the following option.

Code:

saveOptions options save=allpub subcktprobelvl=3 saveahdlvars=all

The tool versions are IC 6.1.4.500.9, and spectre sub-version 10.1.0.213.isr1.

What's wrong? Any comments are appreciated.

Thanks
Yawei

Title: Re: One variable inside a verilog-A module not saved
Post by Geoffrey_Coram on Dec 1^st, 2010, 8:30am

If you make halfref an array, does it disappear also? Or does it give you a hint on how the signal is named (halfref_bit0 or something)?

Title: Re: One variable inside a verilog-A module not saved
Post by ywguo on Dec 5^th, 2010, 6:30am

Hi Geoffrey,

Yes, it disappears if I make halfref an array, like halfref[0:1]. So I create another integer variable named dat instead of vd[0:`NUM_ADC_BITS-1]. Thanks.

Yawei

Title: Re: One variable inside a verilog-A module not saved
Post by Andrew Beckett on Jan 2^nd, 2011, 2:35am

Yawei,

There is a CCR (and a few duplicates) for this - 602394. You might want to get a duplicate filed to increase the likelihood of this being done sooner rather than later.

Regards,

Andrew.