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https://designers-guide.org/forum/YaBB.pl Design Languages >> VHDL-AMS >> Warning messages related to latches https://designers-guide.org/forum/YaBB.pl?num=1291283208 Message started by PabloSistemas on Dec 2nd, 2010, 1:46am |
Title: Warning messages related to latches Post by PabloSistemas on Dec 2nd, 2010, 1:46am Hi there, I've developed a code for a register which takes the values present at its two inputs named "input_1" and "input_2" when the value of the input "flanco_subida" is '1' and shows at the output the values taken from these two inputs until a new '1' appears at "flanco_subida". The code I've written is shown below Code:
The problem that I have is that, when I compile my code with Quartus II, I get a message saying "Warning: Timing Analysis is analyzing one or more combinational loops as latches" / "Warning: Node "SampleHolder|output2|combout" is a latch". If I change the line output_2 <= input_2 WHEN tEstadoActual = EDetectado ELSE '0' WHEN tEstadoActual = EInicio; for output_2 <= input_2 WHEN tEstadoActual = EDetectado ELSE '0'; the warning message disappears, but, as expected, the behaviour of the system is not as desired. Help from anyone? Thanks so much |
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