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Message started by .matteo on Dec 3rd, 2010, 2:43am

Title: tiles on my RF layout
Post by .matteo on Dec 3rd, 2010, 2:43am
Hi everybody,
I just finished the layout of my chip and sent it to the foundry. The design is up to 18GHz.

They sent it back to me covered with tiles to set the density properly over all the chip.

Tiles are everywhere except over inductors (they have the noTile mask of course). Some of them are under some long high frequency M7 interconnections. Others are metal lines over the transistors.

I think the tiles are going to create problems because the signal can couple through them.

What do you think? Do you think I shoult put a noTile mask everywhere?

I've another question: what happens to the magnetic flux that couples into floating metals? Can this create problems if they are coupled to something else?

Thanks a lot,
Matteo

Title: Re: tiles on my RF layout
Post by Frank Wiedmann on Dec 3rd, 2010, 4:59am
The foundry probably won't let you put the noTile mask everywhere, but I think you should try to put it over the high-frequency signal path (and possibly other sensitive areas).

Title: Re: tiles on my RF layout
Post by .matteo on Dec 3rd, 2010, 5:49am

Frank Wiedmann wrote on Dec 3rd, 2010, 4:59am:
The foundry probably won't let you put the noTile mask everywhere, but I think you should try to put it over the high-frequency signal path (and possibly other sensitive areas).

Ok, that's what I'll probably do, of course I cannot put the noTile mask everywhere.

What if I have a M3 signal line with a M2 floating line under it. What happens to the total capacitance to the substrate? I did a simulation and it increases, I dont understand exactly why.

Title: Re: tiles on my RF layout
Post by Frank Wiedmann on Dec 3rd, 2010, 7:05am
Are you sure that it's a good idea to have M2 floating? I'd rather make a low-ohmic connection to a quiet ground or supply (assuming that the M3 line is differential).

When you have a floating conductor between two capacitor plates, their effective distance is essentially reduced by the thickness of the conductor, so the capacitance increases.

Title: Re: tiles on my RF layout
Post by .matteo on Dec 3rd, 2010, 7:34am

Frank Wiedmann wrote on Dec 3rd, 2010, 7:05am:
Are you sure that it's a good idea to have M2 floating? I'd rather make a low-ohmic connection to a quiet ground or supply (assuming that the M3 line is differential).

When you have a floating conductor between two capacitor plates, their effective distance is essentially reduced by the thickness of the conductor, so the capacitance increases.


You're totally right, I just realized it. Thank you very much for your help!
I'm placing noTile masks where they cannot tile and using a "smart tiling tool" to place tiles everywhere else. Hope I pass the DRC density rules..  ::)

Title: Re: tiles on my RF layout
Post by carlgrace on Dec 3rd, 2010, 8:30am
Matteo,

Putting fill blocking layer over your M7 signal lines is a very good idea!  You may have some troubles meeting minimum density rules though if these signal lines are big and are used over a large part of the chip.

Is M6 a thick metal in your process?  If so and you are having problems meeting density you can consider only block the thick metals underneath your wires.  It is usually no trouble meeting global density requirements on the thick metals because you are using them for power routing and such.  It may be an issue on local density depending on the window size in your process.  

I say this because the thin metals really don't make too much of a difference, particularly if you have a single-ended circuit.  I built a 6 GHz LNA about 2 years ago in 65nm CMOS and I was forced to allow fill underneath signal wires and capacitors.  What, I did was to build my own layout cell that had the minimum allowable metal density, then I tiled it under my MIMCAPS and thick metal routes.  I found that the autofill routine put down more metal than necessary and also caused a little bit of mismatch between differential capacitors.  My LNA came back from fab working great.

Good luck,
Carl

Title: Re: tiles on my RF layout
Post by .matteo on Dec 6th, 2010, 12:11am

carlgrace wrote on Dec 3rd, 2010, 8:30am:
Matteo,

Putting fill blocking layer over your M7 signal lines is a very good idea!  You may have some troubles meeting minimum density rules though if these signal lines are big and are used over a large part of the chip.

Is M6 a thick metal in your process?  If so and you are having problems meeting density you can consider only block the thick metals underneath your wires.  It is usually no trouble meeting global density requirements on the thick metals because you are using them for power routing and such.  It may be an issue on local density depending on the window size in your process.  

I say this because the thin metals really don't make too much of a difference, particularly if you have a single-ended circuit.  I built a 6 GHz LNA about 2 years ago in 65nm CMOS and I was forced to allow fill underneath signal wires and capacitors.  What, I did was to build my own layout cell that had the minimum allowable metal density, then I tiled it under my MIMCAPS and thick metal routes.  I found that the autofill routine put down more metal than necessary and also caused a little bit of mismatch between differential capacitors.  My LNA came back from fab working great.

Good luck,
Carl


Thanks for your suggestions Carl!
M6 is thick in this process but I'm using it to take high freq signal around in the chip, not only for power routing.
Your idea to build your own cell that meets the min density rules is good. I think I'll send it back to the foundry with the blocking layers, see if they manage to meet the density rules and if not - hope doesnt happen, I'll do as you did :)
Have a good day
Matteo

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