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Modeling >> Behavioral Models >> analog module instantiation in Verilog AMS
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Message started by priyanka on Dec 3^rd, 2010, 8:13am

Title: analog module instantiation in Verilog AMS
Post by priyanka on Dec 3^rd, 2010, 8:13am

Hi,

I am a beginner at Verilog AMS and need some help with analog module instanitation.

I would like to know how to instantiate a module with analog disciplines (such as electrical ) multiple times. I use a 'generate' construct for this purpose. However, the simulator gives an error as follows:
"<Module name> has got declared analog discipline "electrical". Use of analog element inside Generate statement is not yet supported"

Please let me know how can I have multiple instantiations for an analog block.

Thank You!

Title: Re: analog module instantiation in Verilog AMS
Post by jerome_ams on Dec 3^rd, 2010, 8:53am

Hi,

As far as I know, you do not it to use any generate syntax to instantiate analog blocks.
Do you want to instantiate them within "if - else" statements?
Can you tell a bit more about your code/intentions?

Cheers,
Jerome

Title: Re: analog module instantiation in Verilog AMS
Post by priyanka on Dec 3^rd, 2010, 9:08am

Hi,

There are no if-else statements. I have a basic module called "tdc" which is analog in nature. My system contains several TDCs (in the order of hundreds) and it would be tough to declare them manually. Therefore, I use 'generate' construct.

I need to process the outputs of all TDCs and my signal t_out is used for this purpose. My intention is to analyze few parameters at system level. But I am not able to instantiate the TDC block several times at the top level.

My code snippet is as follows:

wire [0:79] t_out;

generate
genvar q;
for(q=0; q < 10; q = q+1) begin: I_mod
tdc t0 (.start(start), .stop(stop), .out(t_out[8*q : (8*q + 7) ] ) );

end
endgenerate

Such a code gives the following error during elaboration:
"tdc I_mod[0] has got declared analog discipline "electrical". Use of analog element inside Generate statement is not yet supported"

I hope I was able to convey my problem. Please let me know if it is possible to do it any other way!

Thank You!

Title: Re: analog module instantiation in Verilog AMS
Post by jerome_ams on Dec 7^th, 2010, 5:52am

Hi,

please check the code I ve attached.
That s an example taken from
Cadence® Verilog®-AMS Language
Reference
Product Version 2.0
November 2001

It seems it was supported in 2001... They might have removed this feature, but that would suprise me.
Let us know if it works!

Title: Re: analog module instantiation in Verilog AMS
Post by jerome_ams on Dec 7^th, 2010, 5:53am

here the attachment

Title: Re: analog module instantiation in Verilog AMS
Post by jerome_ams on Dec 7^th, 2010, 5:58am

I ve just found out that they actually did planned to replace the "generate" statment by a "for" loop that uses a "genvar" index... But I do not more on this...

hope it helps,
cheers
jerome

Title: Re: analog module instantiation in Verilog AMS
Post by priyanka on Dec 7^th, 2010, 6:06am

I have tried the code as you have shown. The difference is that the direct analog assignments work (as you have shown) but if they are instantiated within a module, it is not supported i.e. multiple instantiations of analog modules is not supported.

Please let me know if i am wrong in my understanding.

Thank you for your time!
Best,
Priyanka

Title: Re: analog module instantiation in Verilog AMS
Post by Marq Kole on Dec 8^th, 2010, 2:20am

The generate constructs in Verilog-AMS are a version 2.3 feature and not supported in most analog and mixed-signal simulation tools. That's too bad given the fact that the standard has been around for over 3 years now and still large pieces of it are not available at all and only a few pieces (the low-hanging fruits, apparently) have been implemented.

In my view the only alternative that is available is to replace the instances by their behavioral code in a for loop (the analog generate loop shown in the example above is obsolete since version 2.0 and has been replaced by the analog for loop).

Marq

Title: Re: analog module instantiation in Verilog AMS
Post by priyanka on Dec 8^th, 2010, 2:33am

Thank you for your reply! Yes, manual instantiations of the block are the other option which I finally chose!

But given that the standard is built for analog and digital modules, such a multiple instantiation of analog blocks should be supported in the first place.

I hope it is integrated soon!

Cheers,
Priyanka