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Design Languages >> Verilog-AMS >> Verilog AMS capability
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Message started by haykp on Dec 6^th, 2010, 1:09am

Title: Verilog AMS capability
Post by haykp on Dec 6^th, 2010, 1:09am

Dear Forum,

Currently I am designing the retention flop and need to calculate the wake-up time but hspice is not good for that. My belief is that I can model the "Z" state of the circuit by verilogA. But I am new in Veilog Ams, and to be honest I am not very familiar with verilogA.

Could you please let me know what capabilities give VerilogA forworking with Z values in the scheme, does it similar to usual verilog?

Thanks

Title: Re: Verilog AMS capability
Post by Marq Kole on Dec 8^th, 2010, 1:21am

Verilog-A and Verilog use different concepts to handling signals - Verilog-A is close to Hspice built-in model in that it uses real-valued voltage and currents that are evaluated at every time-step of the simulator. Such a signal does not know about 'Z' (or 'X', '0', or '1' for that matter) - it depends on the connections to the rest of the design and on the loading and driving impedances at these connections.

What simulation environment do you intend to use? Why is Hspice not good for determining wake-up time? Do you do RTL or transistor-level?

Cheers,
Marq

Title: Re: Verilog AMS capability
Post by haykp on Dec 8^th, 2010, 2:55am

Dear Marq,

Thanks for the feedback,

The hspice is not good, because by hspice I cannot see the exact Z state by waves, so it is very hard to calculate the Z-to-1 time by hspice. And there is no way to write a measure for that.

I am designing in transistor level.

Title: Re: Verilog AMS capability
Post by Marq Kole on Dec 8^th, 2010, 7:22am

The distinction between 'Z' and '1' at transistor level can only be made in a test bench that loads the output. For instance, a small current-source load would start to pull a 'Z' state down while a '1' state stays up. By detecting the onset of the pulldown for a '1'-to-'Z' or the onset of a pullup for a 'Z'-to-'1' you can determine the wake-up time. If you do this for two or three values of the load current, you should be able to determine the wake-up time and its dependency in the load (or fan-out).

That's how I would approach the problem, at least. I think you can capture this in .measure statements without a problem.

Cheers,
Marq