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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> piplelined ADC /OTA dynamic error https://designers-guide.org/forum/YaBB.pl?num=1292359289 Message started by ontheverge on Dec 14th, 2010, 12:41pm |
Title: piplelined ADC /OTA dynamic error Post by ontheverge on Dec 14th, 2010, 12:41pm Hi, in a N-bit pipelined ADC, stage k for example, what should be the dynamic error requirement during its settling period for the MDAC? I think 1/(2^N) is over constrained. any thoughts on this? also, in estimating the slew time, is there any rule of thumbs or we just use (V_step - 2*sqrt(2)*V_overdrive)/SR(input) ? thanks, Steve |
Title: Re: piplelined ADC /OTA dynamic error Post by vivkr on Dec 15th, 2010, 7:24am ontheverge wrote on Dec 14th, 2010, 12:41pm:
what makes you think that the requirement 1/(2^N) is too restrictive? If you consider the systematic DNL introduced at the boundary of each quantization interval, then you will see that a finite settling accuracy dv will appear as +dv on one side and -dv on the other, giving you DNL = 2*dv, just due to finite settling errors (combination of finite DC gain + settling errors). And that would be just the DNL from one single stage. If all your stages were identical, you would get input-referred DNL: = (2*dv + 2*dv/2 + 2*dv/2^2 + ...)/2, where the assumption is that you are using a stage gain of 2. You can work out what dv needs to be in order to get whatever target DNL you want due to systematic errors alone, not counting other error sources. Vivek |
Title: Re: piplelined ADC /OTA dynamic error Post by ontheverge on Dec 16th, 2010, 4:26pm vivkr wrote on Dec 15th, 2010, 7:24am:
I'm thinking of "per stage resolution" which obviously is smaller than N. |
Title: Re: piplelined ADC /OTA dynamic error Post by carlgrace on Dec 17th, 2010, 3:19pm ontheverge wrote on Dec 16th, 2010, 4:26pm:
The key is not the "per stage resolution" but only the resolution remaining after the stage in question. The reason we can scale stages is because the number of remain stages decreases as we go through each pipelined stage. So, a large per stage resolution reduces settling requirements because there are few bits to resolve after the first stage. On the other hand, the feedback factor of the MDAC goes down with larger resolution, so you may need to burn more power to meet even this reduced requirement. |
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