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Design >> Analog Design >> mismatch requirement calculation of the 1st stage of pipeline
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Message started by icisee on Dec 15^th, 2010, 8:15pm

Title: mismatch requirement calculation of the 1st stage of pipeline
Post by icisee on Dec 15^th, 2010, 8:15pm

How to calculate the mismatch requirement of the 1st stage of Pipeline ADC for INL less than 2 LSB?

2.5 Bits/stage (M=3)
Resolution:12bit (N=12)
Vref: 1V (Vref=1V)
Swing(diff):2Vpp (Vsw=2V)

Any advice or reference paper are welcome.

:)

Title: Re: mismatch requirement calculation of the 1st stage of pipeline
Post by carlgrace on Dec 17^th, 2010, 3:14pm

Search for PhD theses of Cho and Abo.