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Design >> RF Design >> RF layout: WPE effects
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Message started by Ruritania on Dec 28^th, 2010, 12:43pm

Title: RF layout: WPE effects
Post by Ruritania on Dec 28^th, 2010, 12:43pm

Hi,

In order to reduce the WPE effects, it is generally advised to increase the distance from the transistors to the well edges. I'm wondering whether the substrate contacts also deteriorate the effects? e.g., for NMOS transistors, the substrate contacts have to be P+ implant - while forming the NMOS S/D, there should be photoresist to stop N+ implanting at the substrate contacts region (P+), thus introducing WPE effects with the same way as the N-well?

Thanks for attention!
Ruri :-?

Title: Re: RF layout: WPE effects
Post by Berti on Jan 18^th, 2011, 6:35am

Hi Ruri,

I am not the expert for this kind of question ...

... but since the penetration depth of the high dose implant process for wells is much deeper compared to the medium dose implant process for the diffusions and contact regions, I think that proximity effects of substrate contacts are much less severe than WPEs.

For more details on sub-65nm CMOS, I recommend the book series from Wong: "Nano-CMOS circuit and physical design" etc.

Cheers