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Design >> Mixed-Signal Design >> How to verify FracN PLL Prescaler functionality
https://designers-guide.org/forum/YaBB.pl?num=1293589725

Message started by gggould on Dec 28^th, 2010, 6:28pm

Title: How to verify FracN PLL Prescaler functionality
Post by gggould on Dec 28^th, 2010, 6:28pm

Hi all,
I am designing a prescaler to provide divide ratio from 2 to 255 for 4GHz vco clock. Basically that is just a cascade of 7 cml_divide_by_2/3_cell.

Does anyone know what test cases should I run to verify the prescaler design in detail? Like which divide ratio(s) can stress the circuit most? How to check if prescaler works under dithering scenario?

Thanks and happy holiday
gggould