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Design >> Analog Design >> Vertical PNP in BGR:The base(nwell) is tied to gnd,so Calibre gives ERC error
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Message started by mix on Dec 29^th, 2010, 7:19am

Title: Vertical PNP in BGR:The base(nwell) is tied to gnd,so Calibre gives ERC error
Post by mix on Dec 29^th, 2010, 7:19am

Hello everyone from a new member,
Congrats for this amazing effort!!

I am currently designing a bandgap reference (BGR) circuit in IBM cms9flp.

Using Assura for LVS the circuit is shown to be correct (layout schematic match, and no extraction problems)

When I use Calibre the result is Correct again, there are no extraction problems, BUT there is an ERC error. The description of the error is:
ERC2
All NWELL Regions should be tied to POWER or most positive chip supply. FRom LVS deck, NWELL = NW NOT (N3 OR NWRES OR NW_RES)

but it points to my vertical pnps (I have taken care to properly bias the nwell all the PMOS in the circuit)

The base of the vpnp pcell is connected to the nwell. But in BGR circuits the collector and the base are both connected to ground. So, this nwell is connected to ground, and not to a POWER net, and thus, I get the ERC error.

But I believe there would be no problem in practice, since the collector (that is the substrate) and the base (that is the nwell) are both connected to ground, and thus the parasitic substrate-nwell diode will never get forward biased and conduct current.

According to this rule, I would get no error only if I connected the base of the vpnp to a POWER net eg VDD, but then the vpnp would be a useless device!! (because Veb would be zero or negative)

I think that there should be an exception in this rule, when the nwell belongs to a vpnp.

Has anybody faced this problem again?
I would appreciate if you shared your view on this issue.

Thank you very much in advance,
mix

Title: Re: Vertical PNP in BGR:The base(nwell) is tied to gnd,so Calibre gives ERC error
Post by ssahl on Jan 4^th, 2011, 11:39am

Hi mix!

It sound like you have connected the vpnp correctly. Of course you can not connect the nwell to vdd in this case.

The simple answer is that there is an error in your Calibre ERC rule file. I have a vague memory from when I worked with a rf-cmos process from TSMC that there was an exception rule allowing tying the collector of the vpnp to the substrate. The exception was that normally this was not allowed, unless it was used in a bgr.

So, probably there is a similar exception rule in the IBM process. If not, you can not build a bgr! But as I said, you are passing the Assura rules but failing the Calibre ones. I recommend that you are get in touch with IBM to solve the issue.