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Design >> RF Design >> achievable IIP3 for cmos passive mixer
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Message started by kelly on Jan 3^rd, 2011, 10:11pm

Title: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 3^rd, 2011, 10:11pm

Hi all,

Can someone comment on the achievable IIP3 for a cmos passive mixer (just the fets switching pairs)? I am using 65nm process with LO power of 17dBm and pretty big FET sizes. The FETs are also biased at sub-threhold at DC. I can't seem to get IIP3 higher than 21dBm over pvt (it's more like 20 to 21dBm). But from reading some papers, it sems that I should be able to get much higher IIP3 with LO>15dBm.

Did I miss something?

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by RFICDUDE on Jan 5^th, 2011, 3:05pm

The numbers you are getting seem reasonable from what I have seen.

What references are you seeing higher IIP3?

The primary 3rd order contributor is Ids nonlinearity as Vds increases, so anything you can do to minimize Ron should help to reduce nonlinearity (wider device, optimized LO drive and proper gate bias).

Also, make sure you are using a model that properly models nonlinearity at Vds_dc=0V. BSIM used to have some discotinuous functions around Vds=0 that yielded bogus linearity results. The PSP model used continous functions through Vds=0 and yield more reliable results. Although, maybe the BSIM model has been updated (I don't know).

Title: Re: achievable IIP3 for cmos passive mixer
Post by aaron_do on Jan 6^th, 2011, 6:28am

Hi,

just curious, +17 dBm seems to be quite high for the LO power. Is that into 50 ohm? That's something like 4 Vpk-pk into 50 ohm so I wonder how the transistor handles it.

cheers,
Aaron

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 6^th, 2011, 11:38am

Hi RFICDUDE and Aaron,

Thanks for replying. Sorry , I didn't make it clear, in oder to have LO of 17dBm, I do need to use the thick oxide devices that can tolerate a voltage up 2.5V across the oxide.

When I use the qpss and qpac to get my IIP3 plot, I have the same problem as Aaron posted before, i.e., the 3order slope looks weired at low input level. Since my IIP3 is around 20dBm, my slope starts to act funny below 0 dBm. I did use the conservative setting for running qpss, but it didn't seem to change my results that much. In general, the slope seem to look ok for the top 20 dB input range. In another word, if the IIP3 is 25dBm, then the 3 order slope starts to behave funny below 5 dBm. So if you try to extrapolate the IIP3 at Pin < 5dBm, you get pretty lousy number, not to mention the slope looks all wrong.

Do you guys think this is a simulation/modeling problem? Or in reality, the IIP3 is that bad at the low input level?

Thanks much.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by vp1953 on Jan 6^th, 2011, 2:37pm

Hi Kelly,

I was just curious - what are the DC bias values at the RF and IF ports?

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 6^th, 2011, 5:54pm

Hi Vp1953,

The RF and IF are biasd at 400mV to 600mV below the LO port (just right before the threshold). I was able to get pretty good conversion loss around -3ish over corner. But my NF is around 8dB. Any idea why the NF is not closer to the CL? Is it just all device noise?

Title: Re: achievable IIP3 for cmos passive mixer
Post by aaron_do on Jan 6^th, 2011, 10:12pm

Hi Kelly,

it would help a lot if you showed us the schematic and the IIP3 simulation results. But if you don't want to, I understand. Anyway, for the NF, why don't you print a noise summary to see which devices are the main contributers to the output noise. You may find that one of the big contributers is not something you expect. Also, I guess you are talking about single-sideband NF?

cheers,
Aaron

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:12am

Not sure whether the attachment will show up

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:14am

OK, I guess I don't know how to attach more than one files, so I'll just do them separately. Here is the top level test bench with LO and RF ports

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:16am

Here is the how the FETS are biased. The resistor divider provides VCC/2 for the Gate. The sources and drains are bias to a voltage thats 400mV below the gate (via the 4 resistors that are connected together)

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:17am

Here are the FET switches. They are 10u/0.26u with M=40 each !

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:26am

Hi Aaron,

I looked at the noise summary they looks ok, no big surprise. The top contributer is the 50 ohms inside the port. The the 4 FETs. If I take the input referred divided by the 4kt(50)/4 (4 is due to the resistor divider form by the 50 ohms source and the 50 ohms to ground at the RF port), I get roughly 8dB which is the same as the NF from Pnoise sim. Yes, I am looking at SSB.

I did notice that there is a slight difference between the conversion loss (-2.85 dB) vs the transfer function from the NF calculation (around -4dB). Don't know why the difference, but even with CL=-4, the NF is still 4 dB higher.

Do you usually see a much closer relationship between CL and NF?

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:50am

OK, this is the IIP3 sim with the same setting and everything as the 1st one I posted earlier, except the FET switches subs are connected to it's respective source (instead of ground). So I expect the IIP3 to improve, which it does, due to smaller threshold voltage. But I don't understand why it craps out at higher input level and the slope seems to look even funkier at lower input level. Do you think this is real, or just simulation? Maybe it's not good to have the sub tie to the source (where the RF is comming in)?

Sorry about all the long questions. I am new at this. Really appreciate all the help from everyone.

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by Andrew Beckett on Jan 7^th, 2011, 5:08am

This is probably the problem that RFICDUDE mentioned earlier.

See: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1358719

Regards,

Andrew.

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 9:36am

Hi Andrew,

Thanks for the paper.

The paper shows that the problem shows up when the IM3 exhibit a slope of 2 insted of 3. The fact that I do get a portion of slope of 3 just not at lower input level for the 1st plot, does that indicate maybe the problem I am having is differernt?

The 2nd IIP3 plot with the device bulk tied to drain also have a small region where the slope is right, just not a very wide range. This one I don't know whether is the model probelm, or I can't tie the bulk to RF with the big swing.........

Has anyone seen what I am seeing before?

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by Andrew Beckett on Jan 7^th, 2011, 10:22am

Maybe, although in general you'd expect that the IM3 curve would get closer to 3dB/dB for lower input powers, and maybe flatten due to numerical noise limits. I've certainly seen similar strange behaviour in passive mixers. This is something we've spent quite a bit of effort in trying to solve (by altering the models to see if that can help). Certainly the problem doesn't happen with psp models (if it's this issue).

What are your accuracy settings in the simulator (in particular errpreset and reltol) - in fact might be easiest just to post the section at the top of the RF analysis which lists the "important" settings?

Regards,

Andrew.

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 12:11pm

Hi Andrew,

these are my setttings,
in the analog option
reltol =1e-6, vabstol=1e-10, iabstol=1e-12, the rest is default
in the qpss,
shooting
conservative

I did find out that in the case when I tied the bulk to source, there are times that the source(bulk) to gate is forward biased by a 1V when Prf =11dBm.

But do you think my 1st IIP3 plot also looks funny too?

In your design, do you tied the bulk to source or you usually just let it at ground?

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by ssahl on Jan 7^th, 2011, 12:29pm

Hi kelly!

I have followed this thread with interest for a while. As several people has pointed out there is a weakness in the BSIM models for this applications, that is when the signal swing passes Vds=0. I strongly advise you to check which model you are working with. You should not use the BSIM one. The PSP is a much better choice in this case. I do not think you ever will get a 3/1 dB slope with the BSIM model. If you simulate only the mixer transistors standalone and measure Id when sweeping Vds from negative to positive values you will see a discontinues in some of the derivities of the current.

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 1:06pm

Thanks. I'll check on that.

Title: Re: achievable IIP3 for cmos passive mixer
Post by vp1953 on Jan 7^th, 2011, 3:26pm

Hi Kelly,

should not the DSB NF be considered here ? - in this case the NF is very close to the CG.

What is frequency for the NF and CG values?

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 7:35pm

Hi Vp1953,

aahh, because in the normal lossy network (where NF=loss), there is no noise folding from the image band, that's why we should compare DSB NF to the CG instead of the SSB NF?

I measure both NF and CG at 200M since Flo and Frf are 1.8G and 2G, respectively.

Thanks!

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 8:03pm

Hi Ssahl,

I did check my model and you are right, I am using BSIM4. No one is aware of the non-leaniarity modeling issure aroubd vds=0. Doesn't seem like there is PSP model for now.......I guess I'll run the sim you suggested to see whether that still exists in the present model.

I have a questions then, assuming the P1dB sim is accurate (since it's just the fundemental tone), can I just estimate IIP3 be roughly P1dB+9.3 (something like that). I have noticed that in some passive mixer papers, they just quote the P1db simulation data instead IIP3. In another words, you often see the spectre IIP3 curve for active mixer papers, but rarely see that for the passive mixer ones.

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by aaron_do on Jan 7^th, 2011, 9:53pm

Hi Kelly,

I don't think that you can simply add 9.3 dB to your P1dB. The assumption there is that 3rd order nonlinearity dominates the compression, but your third order nonlinearity is not correct. Also, for your mixer, you need to decide what kind of image rejection scheme you are going to use. If you are using filtering with a high IF, then SSB NF is correct. Otherwise you should use DSB NF, and in that case, the mismatch is only 1 dB. This could easily be due to other noise sources.

cheers,
Aaron

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 7^th, 2011, 10:20pm

Hi Aaron,

I remember you had an earlier post where you included a similar IIP3 plot like my 1st one. Did you ever resolve your problem at the low input level? Was it an accuracy thing or model? Also have you ever compared the qpss and qpac results with a two tones transient test? Do they match?

Can you explain what you mean by which NF to use depending on what image filtering scheme you have? Do you mean the filtering scheme in the real sysytem or as part of the simulation?

Thanks much!

Title: Re: achievable IIP3 for cmos passive mixer
Post by vp1953 on Jan 8^th, 2011, 11:50am

Hi Kelly,

Quote:

aahh, because in the normal lossy network (where NF=loss), there is no noise folding from the image band, that's why we should compare DSB NF to the CG instead of the SSB NF?

Yes, thats what i was thinking.

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 8^th, 2011, 10:31pm

Hi vp1953,

Is there any situation you will use SSB NF (to compare to CG) then?

Thanks.
Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 9^th, 2011, 1:23am

Hi all,

I think I finally understand (I hope) what you guys have been trying to tell me. Please see the IIP3 plot attached.

This is obtained by having the gate(LO), drain(IF) and source(RF) all biased at the same DC bias voltage, i.e. the drain/source are not biasd below the gate just below the threshold. Sure enough, you can clearly see the non-3db/db slope. My 1st IIP3 plot attached earlier (please see page 1), was obtained with the drain/source biased 400mV below the gate i.e., the devices are more on than the 0 bias case. I think that's why the problem of non-3db/db slope problem does not show up as prominantly as the one attached in this post.

I also obtain the same results using the harmonic balance method. Just as a reference, the model I am using is BSIM4(V4.5).

So I guess this pretty much conclude my IIP3 sim questions. By the way, the other simulations such as noise, s-parameters are still valid, as this modeling deficiency only affects the IM3 sim, right?

Please correct me if I am wrong, and thanks for all your patience.

Kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by aaron_do on Jan 9^th, 2011, 6:17am

Hi Kelly,

I guess you already have your answer about the NF. In case you are using a high IF, your mixer is probably after an image reject filter. In this case SSB NF is valid since the image noise is filtered before it folds.

Oh yeah, in answer to your question about my previous post, I don't really remember which one you are referring to, but one of the times I asked it was due to the numerical accuracy of the simulator (hence use conservative setting), and the other time it was due to the asymmetric modeling of the BSim model.

cheers,
Aaron

Title: Re: achievable IIP3 for cmos passive mixer
Post by vp1953 on Jan 9^th, 2011, 1:53pm

HI Kelly

Quote:

Is there any situation you will use SSB NF (to compare to CG) then?

Yes, as stated by Aaron_do already.

Title: Re: achievable IIP3 for cmos passive mixer
Post by ssahl on Jan 14^th, 2011, 9:57am

Hi kelly!

I was claiming in an earlier post that there is a discontinuty in the BSIM3 model. I hooked up a nmos transitor in the linear region, swept the Vds from -0.4 to +0.4V and measured Id thrue the transistor.

The attached plot shows Id, the first and second derivities of it. You see the discontinues I was describing. If you are using qpss with the RF signals as moderate signals qpss tries to linearize around the discontinues point, which is not possible. Therefor you get problems with the 1:3dB slope.

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 14^th, 2011, 2:36pm

Hi ssahl,

Thanks. I verified the same Ids_vds characteristics with the BSIM4 mode I am using too.

With the absence of the PSP model, do you know how much off is the IIP3 from BSIM compared to that obtained from PSP? Is the P1dB from BSIM still correct though?

Thanks.
kelly

Title: Re: achievable IIP3 for cmos passive mixer
Post by ssahl on Jan 14^th, 2011, 2:51pm

Hi kelly!

I think it is very hard to say how much off the IIP3 simulations are. To give an answer one has to understand how qpss is working. What you can do is to apply a real two-tone test with a transient analysis and measure the IM3 levels with a fft. If you sweeping the power you will also see the P1dB. Maybe this take longer simulation time but you vill modulate the nmos mixer with a real signal.

Title: Re: achievable IIP3 for cmos passive mixer
Post by kelly on Jan 14^th, 2011, 11:34pm

hi ssahl,

please see
http://www.designers-guide.org/Forum/YaBB.pl?num=1286953333

If I understand it correctly, the shooting method should give you the same answer as the transient. HB, on the other hand, it's a little different.

I am just wondering since the Ids is ok, shouldn't the P1dB result with BSIM be ok?

Thanks.

Title: Re: achievable IIP3 for cmos passive mixer
Post by Andrew Beckett on Jan 15^th, 2011, 11:08am

I think the P1dB should be OK, because at higher input powers things behave OK (from what I've seen).

I don't think transient would solve the problem with the IIP3 sim - if I've understood the effect properly (and sorry, I've not looked deeply into this for a while). The discontinuity should affect that too, I believe.

Regards,

Andrew.

Title: Re: achievable IIP3 for cmos passive mixer
Post by ssahl on Jan 15^th, 2011, 12:59pm

After some more thinking I agree with Andrew that the discontinuity problem should be there even for the transient case. The problem is that the BSIM3 model is non-physical around Vds=0. But I also believe that simulation methods that tries to linearise around the qusient point are more sensitive to this model problem. So, transient and pss with shooting would be least sensitive, HB and qpss next, and rapidIP3 most sensitive, I would guess.