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Modeling >> Behavioral Models >> Bidirectional shift register: continuous time modelling in Verilog A
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Message started by mrxyzlinkoping on Feb 1^st, 2011, 10:45am

Title: Bidirectional shift register: continuous time modelling in Verilog A
Post by mrxyzlinkoping on Feb 1^st, 2011, 10:45am

Hello evryone,

I have two queries which I am listing below:

1.
I am trying to model a verilog A model of continuous time bi directional shift registers.
Based on the input signal and clock the output can be either incremented or decremented by one (normal bi directional shift register operation).

I have clock and input signal as my input and N (variable = 8 to 512) output ports. All in continuous time. There is no sampling done anywhere. The clock mentioned above and in the code is another signal which is being used as clock to perform the operation (kind of asynchronous operations).

Code I have written is as shown below:

@ (initial_step)begin
for (i=0; i<256;i=i+1)
begin
result[i]=0; // temp location to store result initialize to zero
end

end // initial

@(cross(V(clk)-clkThresh, -1)) begin
sampleIn = V(vIn); // vIn is the input voltage
for (i =0; i<N; i = i+1)
begin
if (sampleIn >=0.5)
begin
result[0] = 0; // first bit set to zero
result[i+1] = result[i]; // rest all shifted right
end
else if (sampleIn < 0.5)
begin
result[i] = result[i+1]; // all bits shifted to left
result[N-1] = 0; // last one set to zero
end
end

// final assignment of the output signal

for (i =0; i<N; i = i+1)
V(srOut[i]) <+ transition(result[i], td, tr, tf);

end module

My problem is I am not able to model the N output ports in verilogA. Final assignment as highlighted in red is throwing parsing error.

'the index used to bits of analog signal vector srOut is constant, constant expression, genvar-constant expression. To avoid this problem, ensure that the index used to access the bits of analog signal is constant, constant expression, genvar-constant expression.'

Can someone please help me to resolve my problem.
Also I ll be glad to provide any information or to clarify any point if not clear above.

2.
In the variable ADC code at http://www.designers-guide.org/VerilogAMS/functional-blocks/data-converter/converter-spectre.vams
can some one please explain me the ussage of following statement:

localparam integer levels = 1<<`bits;

Thanks
xyzLinkoping

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by Marq Kole on Feb 2^nd, 2011, 5:57am

You should use a genvar variable for the for loop in the output section. You can use an ordinary integer for the other for loop.

You do not need to initialize the result[i] values - they always default to 0 in Verilog-A.

The operator you mention is the bit shift. A shift to left means an integer multiplication of an integer value by 2. It is not allowed to use this on non-integer values. You can use this on a genvar, but only inside the heading of a for statement.

Cheers,
Marq

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by Marq Kole on Feb 2^nd, 2011, 6:02am

A bit of explanation: the genvar is needed because this is an analog for-loop. The transition filter inside your for-loop body must be evaluated at every time step exactly the same number of times. The use of a genvar as index variable forces that behavior as the only locations where you can assign a value to a genvar are the index initialization and index update parts of a for-loop:

for (<index initialization>; <index condition>; <index update>) <statement>

Cheers,
Marq

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by mrxyzlinkoping on Feb 2^nd, 2011, 11:17am

Dear Marq,

Thanks for your suggestion. I used genvar for the output loop and it worked. Atleast I am not seeing the error message.
Actually I checked the verilogA manual for defining variables for analog signal, but nothing is mentioned there.

Question came to my mind. Is everything defined for verilog ams works in A version as well?

I have to confirm the functionality of my code... as I feel the output may not be as expected. :)

I'll update whatever is the result after finishing the testing tomorrow.
I have to use it in spectre.

Thanks again
Rgds
DC

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by Marq Kole on Feb 3^rd, 2011, 5:52am

Hi DC,

yes, everything in Verilog-A is also valid in Verilog-AMS. Verilog-A is a defined subset of Verilog-AMS - defined in Annex C of the Verilog-AMS standard.

Cheers,
Marq

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by Marq Kole on Feb 3^rd, 2011, 7:50am

Sorry, reread you question: the answer is no, for exactly the same reason. Verilog-AMS is a superset of Verilog-A. It contains langauge elements that cannot be simulated with an analog solver - you will need a digital event-driven engine to handle these constructs. So if you need to use Spectre, stick to Verilog-A. If you can use AMS Designer (Spectre + NCsim) you can also work with Verilog-AMS but then we're talking about a completely different ball game altogether.

For testing try to make a test bench that can be used both for your model and for your implementation/schematic. That saves on test bench creation effort and allow you to get a one-on-one comparison of the model against the schematic.

Cheers,
Marq

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by mrxyzlinkoping on Feb 3^rd, 2011, 2:08pm

Hi Marq,
Thanks for your reply and suggestion on test bench.

BTW the code is working but not giving the correct output :)
I need to check the logic now... it may not be correct for bidirectional shift register.

Rgds
DC

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by Geoffrey_Coram on Feb 4^th, 2011, 4:59am

I don't see how you ever get a "1" into your shift register (at least, not with the code you originally posted). It looks like you are using sampleIn to determine which direction to shift, but whichever direction it shifts, you set the new data bit to zero (result[0]=0 or result[N-1]=0).

Also, you have that assignment done N times: result[0] = 0 is done inside the for loop. Ah, it's worse than that: for i=0, you set
result[0] = 0;
result[1] = result[0];
then on the next loop, i=1, so
result[0] = 0; // no "i" here, done every time
result[2] = result[1]; // and result[1] was set to zero when i was 0
then, for i=2,
result[0] = 0; // no "i" here, done every time
result[3] = result[2]; // and result[2] was set to zero when i was 1
etc.

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by mrxyzlinkoping on Feb 4^th, 2011, 10:47pm

Thanks Geoffrey_Coram for pointing out the problem in the code.

Can someone help me with some handy snippet of Shift Register modelling in verilog (or infact in any other HDL). It will be really nice.
(Or may be a bit modification in my earlier code which I believe should work with some modification)

Thanks
DC

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by Geoffrey_Coram on Feb 7^th, 2011, 5:30am

// N bit register, indexed 0 to N-1

@(cross(V(clk)-clkThresh, -1)) begin
sampleIn = (V(vIn) >= 0.5) ? 1 : 0; // vIn is the input voltage
dirIn = (V(vDir) >= 0.5) ? 1 : 0; // vDir is the direction

if (dirIn) begin
for (i =N-1; i>0; i = i-1) begin
result[i] = result[i-1]; // shift right
end
result[0] = sampleIn; // new sample
end else begin
for (i =0; i<N-1; i = i+1) begin
result[i] = result[i+1]; // shift left
end
result[N-1] = sampleIn; // new sample
end

end // of cross

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by mrxyzlinkoping on Feb 7^th, 2011, 11:01pm

Thanks Geoffrey_Coram,

I will test it today in my test bench.

Best Rgds
DC

Title: Re: Bidirectional shift register: continuous time modelling in Verilog A
Post by mrxyzlinkoping on Mar 13^th, 2011, 12:45pm

I think I missed to mention here that the code given by Geoffrey worked well (with slight modification as per my requirement)

Thanks Geoffery for the help.

Best Regards
DC