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Design Languages >> Verilog-AMS >> Testbench in Verilog-AMS for LDO
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Message started by nb439 on Feb 3^rd, 2011, 5:20am

Title: Testbench in Verilog-AMS for LDO
Post by nb439 on Feb 3^rd, 2011, 5:20am

Dear all,

I am trinee in Verlog-AMS modeling. I want to model a testbench in Verilog-AMS for LDO. Please help me.

Thanking you,
nanib.

Title: Re: Testbench in Verilog-AMS for LDO
Post by Marq Kole on Feb 3^rd, 2011, 7:54am

I propose you start with putting some effort in the modeling. There are quite a number of helpful people around here, but we're not going to do the work for you.

Cheers,
Marq

Title: Re: Testbench in Verilog-AMS for LDO
Post by nb439 on Feb 4^th, 2011, 12:36am

Thank you Mr. Marq.

nanib