The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Loop Gain
https://designers-guide.org/forum/YaBB.pl?num=1297236051

Message started by Rakesh on Feb 8^th, 2011, 11:20pm

Title: Loop Gain
Post by Rakesh on Feb 8^th, 2011, 11:20pm

Hi all,
I wan to calculate the loop gain when u have transistors in linear region. An example of this is when we have back to back inverters. We have Vdd at one input to inverter and zero at the output of the inverter.

Since the transistors are in linear region we get very small gain from these transistors.
Then how does the positive feedback works..
how to calculate the loop gain.
Should i model the inverters as gm block while calculating loop gain

Title: Re: Loop Gain
Post by buddypoor on Feb 9^th, 2011, 12:15am

Why don`t you post a circuit diagram? Otherwise it is not easy to answer your - more or less general - question.

Title: Re: Loop Gain
Post by Rakesh on Feb 9^th, 2011, 12:37am

Hi, here is the ckt for back to back inv..initially all the transistors are in linear or cut off region...
Agreed during transition we have large loop gain as both behave like voltage controlled current sources...
Wen it is in linear h to calculate loop gain as if we give a small noise at any input who is making that noise to go to zero. Is it because this voltage is on resistor to small signal ground so the charge goes to zero..

Is it correct to say we dont have positive feedback till the trip point

Title: Re: Loop Gain
Post by Garrett.Neaves on Feb 9^th, 2011, 4:34am

Rakesh,

Loop gain is defined with regard to a small signal linearized equivalent circuit. The values of the components in the small signal equivalent circuit are established by the DC operating point of each component in the original circuit. The transistors in the original circuit have small signal equivalent models whether they are operated in the linear region, or the active region or the substreshold region, etc.

Therefore, to calculate the loop gain at a particular DC operating point, I would first determine the small signal equivalent circuit of the original circuit at that operating point. Then analyze the loopgain using the small signal equivalent circuit.

Garrett Neaves

Title: Re: Loop Gain
Post by buddypoor on Feb 9^th, 2011, 4:51am

Yes, I agre with Garrett.
However, it is important if Rakesh wants (a) to derive a formula for the loop gain (based on small-signal models) or (b) if he plans a stability test based on the simulated frequency response of the loop gain.
In case of (a) the task may be somewhat complicated.

Title: Re: Loop Gain
Post by Rakesh on Feb 9^th, 2011, 5:37am

I too agree with garrett. In this case of back to back inverter. what is the operating point as signal will swing all the way to rail as its a positive feedback system. Where to linearize the system to calculate the gm of the transistors.

If we calculate using small signal model we get the loop gain to be very small at the beginning since the transistors are in linear region.

Loop gain will only be high if we linearize the circuit when both the transistors are in saturation regions.

So if we have any noise in the circuit (around Vdd) at one input if we see via loop gain we dont get any modification of noise due to lower loop gain...

However we know noise rather dies out ..
Is is possible to explain in terms of loop gain here.
Is it that due to noise having path to ground or vdd is removed with time.

Title: Re: Loop Gain
Post by Garrett.Neaves on Feb 9^th, 2011, 8:01am

Rakesh,

The post which started this thread included the question "how does the positive feedback work?" since the loop gain is very small when the transistors are biased in the linear region. I think the feedback works if the loop gain is non-inverting and greater than 1.

My understanding of what you are asking with regard to the modification of noise on an input of one of the inverters is not clear enough for me to readily see how to proceed. If I were to address the noise topic further, I would want to get a better understanding with some offline clarification, then bring the discussion back to this forum. I understand that offline discussion may not be of interest to you. I wish you the best all the same.

Garrett

Title: Re: Loop Gain
Post by sheldon on Feb 10^th, 2011, 1:37am

Rakesh,

You are looking at the problem backwards. The latch does not go
out of latch unless forced, for example, by shorting a switch across
the inverters. You solve the problem by assuming that the two inverters
are biased at their switching threshold, i.e., the level of the input and
output the instant after that ever so helpful switch opens. In this case
all the transistors are biased in saturation, both the inverters have
gain, and the loop gain is large, >>1.

Best Regards,

Sheldon

Title: Re: Loop Gain
Post by Garrett.Neaves on Feb 10^th, 2011, 5:16am

It looks like Sheldon understood the question concerning the modification of noise on an input of one of the inverters. I would now add that the loop gain is noninverting and less than 1 when the latch is in the latched state.

Title: Re: Loop Gain
Post by Garrett.Neaves on Feb 10^th, 2011, 5:28am

By the "latched state", I mean that state in which neither gate is being externally forced.

Title: Re: Loop Gain
Post by Rakesh on Feb 10^th, 2011, 5:47am

I agree with sheldon. So when the inverters are in latched state we dont get any loop gain so the latch will not flip.. However any small change at a input to inverter dies due to dynamic node and not due to feedback. is it correct..

So now in the case of designing an latch wat all we need to consider is the gm of the transistors near the noise margin as that would be the initial gm of the latch . If this is high enough then we can have good stability