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Design >> Analog Design >> Mixed Signal Layout - Seperation of VDDA VDD , GND
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Message started by AlexPo on Feb 12^th, 2011, 12:33am

Title: Mixed Signal Layout - Seperation of VDDA VDD , GND
Post by AlexPo on Feb 12^th, 2011, 12:33am

we design a mixed signal chip with three main parts:
- sensible analog
- switched capacitor based adc
- logic part

all these parts are connected to a the padring, which build up by standard digital output cells, and ESD protected analog cells.

Now my question is - how should we seperate the power lines. I know we have to seperate vdd(digital) and vdda(analog) but what should i do with VDDA of SC Circuits and with the power of padring(digital outbut buffer and esd diode connection)

i want to minimize crosstalk and clockfeedthrough to all analog - and to ensure i high snr for adc.

Second question: Should i separate digital ground and analog grounfd, too? How i can to this becaus LVS notice the connection about substrat and give me an error,

Title: Re: Mixed Signal Layout - Seperation of VDDA VDD , GND
Post by loose-electron on Feb 13^th, 2011, 1:27pm

Lots of fancy routing to keep separated grounds generally leads to a pair of grounds that are DC separated, but solidly tied together at the frequencies of interest due to all the parasitics.

Go to:
http://effectiveelectrons.com/HelpIC.htm

Read the two articles on Noise reduction.

Also look at:
http://effectiveelectrons.com/substrate.htm

Those are a start - let me know if you need more info.