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Design >> Analog Design >> Flip flop design
https://designers-guide.org/forum/YaBB.pl?num=1297682011

Message started by haykp on Feb 14^th, 2011, 3:13am

Title: Flip flop design
Post by haykp on Feb 14^th, 2011, 3:13am

Dear Forum,

The attached picture is a schematic diagram of a Dff.

As can be seen in that diagram the first input TG clock is CL and not CLK.

What is the reason of this? Why we cannot conect the CLK to the clock of first TG.

Thanks,
Hayk Petrosyan

Title: Re: Flip flop design
Post by rfidea on Feb 14^th, 2011, 9:51am

Probably to get some buffering and not loading CLK more than necessary.

Title: Re: Flip flop design
Post by Rakesh on Feb 14^th, 2011, 10:57am

Probably for meeting hold time requirements or bufferening the input clock

Title: Re: Flip flop design
Post by vp1953 on Feb 15^th, 2011, 9:09am

Hi Haykp,

You are saying CLK and CL could be used instead of CL and CL-bar. The circuit requires complementary clock signals. CLK is external and may have a large skew depending on the load on the driver; i dont know if there might be some issues using a skewed CLK and a non-skewed CL for the complementary clock signals. Using internally generated CL and CL-bar removes the external clock skew.

Title: Re: Flip flop design
Post by Nandish Mehta on Feb 21^st, 2011, 8:23am

The main concern with all flip-flop design is the clock loading. It is one of the main design metric.

CLK routing and distribution tree already consumes hell lot of power. Add even one TG extra to CLK is majority of time not affordable. Hence CL & CLb are generated first.

If you go through the operation you will find that operation of F/F is still same as with CL or CLK.

Hope this helps
Regards
Nandish