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Design Languages >> Verilog-AMS >> adder in verilog-ams
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Message started by vp1953 on Feb 14^th, 2011, 11:03am

Title: adder in verilog-ams
Post by vp1953 on Feb 14^th, 2011, 11:03am

I wanted to know if verilog-ams supports register addition like in standard verilog. For instance would the following code work in verilog-ams, if not what changes might be needed?

reg [7:0] A,B,C;

assign A=B+C;

Title: Re: adder in verilog-ams
Post by Geoffrey_Coram on Feb 14^th, 2011, 12:44pm

Verilog-AMS is a super-set of Verilog, so it should work. I have a vague impression you can't use reg in the analog block, but it should be OK in a digital section (always, initial).

Title: Re: adder in verilog-ams
Post by vp1953 on Feb 15^th, 2011, 9:20am

Hi Geoffrey,

Thank you very much. I meant to ask if it was possible to implement such an adder in VerilogA. What I want to do is to add two 8 bit numbers and get the sum and carry. However none of the verilogA examples that i have gone through has anything similar (including the models available at designers-guide). Is it even possible to do this in VerilogA?

Title: Re: adder in verilog-ams
Post by Geoffrey_Coram on Feb 15^th, 2011, 1:16pm

Two simulators I tried wouldn't let me have "reg" in a Verilog-A module.

Certainly, it is possible to add two integers together; I guess it comes down to: how do you intend to set B and C, and what do you want to do with A once you've gotten the sum?

Title: Re: adder in verilog-ams
Post by vp1953 on Feb 15^th, 2011, 2:30pm

Hi Geoffrey,

Many thanks. I was also not able to get reg to work. What i want to do is to add A+B and store this in C which is 8 bits and the 9th bit of C i want to use as carry.

Seems like the following is one way

C=A+B;
carry = C & 9'b100000000;
carry = carry >> 8;
C= C & 8'b11111111;

Title: Re: adder in verilog-ams
Post by Marq Kole on Feb 16^th, 2011, 5:58am

Hi,

If you recode it in integer arithmetic it should work fine. working with regs works only well from the digital side. Assignment to regs (procedural assignment) should be done in an always block, not in an analog block. Always blocks are not supported in Verilog-A. Field widths do not have a meaning in Verilog-A as everything is mapped onto integers that have a fixed width of 32 bits.

Your code indeed can be readily used in a Verilog-A analog block. You can leave out the field widths for the literals as they're not honored anyway.

Cheers,
Marq