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Design >> RF Design >> Q on MOM capacitor in TSMC foundry
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Message started by neoflash on Feb 20^th, 2011, 12:03pm

Title: Q on MOM capacitor in TSMC foundry
Post by neoflash on Feb 20^th, 2011, 12:03pm

Starting from 55nm technology, TSMC starting to provide MOM capacitor in generic CMOS technology such as 40LP.

My question is that whether TSMC do any special treatment on those MOM area, to improve the metal width/space accuracy? (which eventually improve capacitor accuracy) Or MOM cap is just a regular metal finger cap which a special layout pattern.

Usually, finest metal spacing will cause metal-metal finger capacitor variation as large as about +/- 20% or even worse. I heard from the street that MOM capacitor accuracy can be within +/- 10%. I'm curious if this is real.

Thanks,
Neo

Title: Re: Q on MOM capacitor in TSMC foundry
Post by philcorb on Feb 28^th, 2011, 6:40am

Hi,

This is an area I am also interested in, especially matching of MOM caps.

I think it is also important to consider the metal height variation, as well as lateral spacing, as significant capacitance comes from the walls. Metal height (vertical thickness) is likely to vary with surrounding metal fill, etc.