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Design >> Analog Design >> High AC PSRR 2+ stage opamp
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Message started by RobG on Feb 22^nd, 2011, 12:16pm

Title: High AC PSRR 2+ stage opamp
Post by RobG on Feb 22^nd, 2011, 12:16pm

Hello,
I have a "funny" design, for me anyway. It is a low-noise LDO that has to supply 1-5 mA with a 10nF load and 2 nV/rt-Hz at 400 kHz. Basically I'm planning on an OTA driving a PFET -- i.e. the obvious approach.

The problem I am having is getting good PSRR at around the 3dB point of the opamp if normal "Miller" compensation is used. This is a well-known problem due to the PFET looking like a diode connected to the power supply at frequencies beyond the opamp bandwidth.

I can't use the normal high-PSRR technique of cascode compensation because the gm of the cascode device is much smaller than the gm of the output FET, so the loop gain peaks.

And there isn't enough room for a source follower, nor can I put the comp cap across gate-source of PMOS device because the load is variable.

So I'm looking for new ideas.... Perhaps some of the new nested compensation techniques are better suited for high PSRR? If the Miller cap was across an NMOS it would be referenced to a cleaner supply. (I can do that with a shunt regulator, but I'm trying to avoid that.)

Rob

Title: Re: High AC PSRR 2+ stage opamp
Post by vivkr on Feb 25^th, 2011, 2:11am

Rob,

Have you considered using Ahuja compensation. Check the JSSC paper from B.K. Ahuja (Dec. 1983)? That one was designed precisely to get rid of PSRR problems. I am not sure if the current consumption and noise of that one are quite suitable for you though, as there is an intermediate level shifting common-gate stage which needs some current to get decent slew rate (might not be an issue for your LDO), and adds noise and systematic offset.

But otherwise, the design is extremely elegant and very easy to compensate.

COuntless variants on the same scheme have been published over the years, mostly trying to merge that CG stage into either the input branch or the output branch as a cascode, but all make the compensation harder as the virtual ground return is no longer as ideal as in the original structure.

Regards,
Vivek

Title: Re: High AC PSRR 2+ stage opamp
Post by Alexandar on Feb 25^th, 2011, 5:05am

Can't you put an resistor in series with the miller capacitor?

Title: Re: High AC PSRR 2+ stage opamp
Post by vivkr on Feb 25^th, 2011, 5:58am

technically yes! and that ought to be better than the direct miller connection at any rate, as far as PSRR goes. But the PSRR there is also not significantly superior, not as much as what you might get with Ahuja compensation, because that one allows you to use a much smaller compensation cap.

Regards,
Vivek

Title: Re: High AC PSRR 2+ stage opamp
Post by RobG on Feb 25^th, 2011, 7:42am

Ahuja compensation is the cascode compensation I was referring to, so yes I tried it. The problem I run into is that the gm of the output device is very large compared to the cascode device so there is frequency peaking. In addition, noise from the cascode device is pretty much directly coupled to the output device via the compensation capacitor.

I tried making the cascode device "active" using gain. This reduces the impedance looking into the source by the loop gain, which works VERY well to kill the peaking. Unfortunately the noise is directly added to the overall noise. Nonetheless, it seems like the best option I have seen as of yet. Unless I stumble across something here...

I'll try putting a resistor in series with the cap again. When I tried it before it was a major noise source at higher frequencies.
rg

Title: Re: High AC PSRR 2+ stage opamp
Post by vivkr on Feb 28^th, 2011, 4:50am

RobG wrote on Feb 25^th, 2011, 7:42am:

Note that the original Ahuja compensation scheme has no cascode, but a separate CG branch which is used for generating the virtual ground return. However several derivatives of the scheme using cascodes appear in the literature under the title of Ahuja compensation.

In my experience, the orginal scheme allows far easier compensation with very few problems related to peaking etc. than any of the cascoded versions as the cascode device is now seeing the signal and trying to realize a virtual ground at the same time, which makes life hard for it.

Please take a look at the original from the JSSC paper. It won't solve all your problems but maybe the compensation.

Vivek

Title: Re: High AC PSRR 2+ stage opamp
Post by RobG on Feb 28^th, 2011, 7:28am

I actually tried it separate but I didn't look to see if the AC response was peaking (I was looking at noise performance). I just assumed... ;)

Seriously, I did not know that peaking was less when it wasn't in the same signal path. Thanks! That is very helpful.

Rob

Title: Re: High AC PSRR 2+ stage opamp
Post by vivkr on Mar 1^st, 2011, 1:25am

You are most welcome! That little bit about returning the feedback current to a signal-independent virtual ground is actually the crux of the paper. The basic problem lies in the additional power consumption and noise added by that extra branch (plus systematic offset in single-ended designs).

I remember having had a hell of a hard time once when I tried to get rid of that extra branch. I could do it, but with a considerably more complicated solution.

Vivek