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Design >> Analog Design >> Low gm/Ids in 0.18um CMOS
https://designers-guide.org/forum/YaBB.pl?num=1299031733

Message started by orient on Mar 1^st, 2011, 6:08pm

Title: Low gm/Ids in 0.18um CMOS
Post by orient on Mar 1^st, 2011, 6:08pm

Hi there,

I noticed that my thick-oxide (3.3V) transistors have a systematic low gm/Ids, when compared to the theory. We need to use a special technology that only offers low-power MOS transistors, which is tricky for some analog designs due to high Vt.

In strong inversion, but not in velocity satuation yet, my transistors should have a gm as

gm = 2Ids/(Vgs-Vt)

At a Vds,sat of 0.2V, for some reson, all my NMOS have 35% lower gm, while the PMOS have even lower gm of 40% with respect to the theory.

Is this normal? If yes, is it related to the high Vt option? Thanks.

Title: Re: Low gm/Ids in 0.18um CMOS
Post by ywguo on Mar 2^nd, 2011, 6:41am

Hi Orient,

The equation gm = 2Ids/(Vgs-Vth) is derived from a first order model of MOSFET which operates in strong inversion region. The real life is not so simple. Most SPICE models adopted by Foundry or IDMs are BSIM3, BSIM4.5, MOS9, MOS11, and so on. Those models usually has around 100 parameters. The equations are very complicated.

I understand that you need bigger gm with specified Ids in a low power design. Please refer to the following paper.

Quote:

F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a Silicon-on-Insulator micropower OTA,” IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1314–1319, Sep. 1996.

You can google Gm over Id. There are some good literatures about the detailed simulation setup and so on. One of those papers is attached here.

Best Regards,
Yawei

Title: Re: Low gm/Ids in 0.18um CMOS
Post by ywguo on Mar 2^nd, 2011, 6:42am

One more

Title: Re: Low gm/Ids in 0.18um CMOS
Post by orient on Mar 2^nd, 2011, 9:43pm

Hi Yawei,

Thanks for the info and papers... The example on how to extract the data from DC operating points was really useful, thanks...

Here in attachment is the gm/Id for my transistors, extract from DC operating points.

I also plotted the theoretical gm/Id. As you can see, the theory is not that bad, and it uses only 3 parameters... however, the techno we are using is systematically worse... I think this is really a bad technology for gm/Id, not simply model mismatch...

Cheers!

Title: Re: Low gm/Ids in 0.18um CMOS
Post by ywguo on Mar 28^th, 2011, 8:31am

Hi Orient,

The x-axis is (V_gs-V_th) in your plot. Did you try to plot gmoverId vs V_gs? You can make V_gs lower than V_th, i.e. the transistor is in the weak inversion region.

Best Regards,
Yawei